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 intel
(R)
Intel(R) 450NX PCIset
82454NX PCI Expander Bridge (PXB) 82453NX Data Path Multiplexor (MUX) 82452NX RAS/CAS Generator (RCG) 82451NX Memory & I/O Controller (MIOC)
Order Number: 243771-004 June 1998
(c) Intel Corporation 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel(R) 450NX PCIset may contain design defects or errors known as errata which may cause the product to deviate from the published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com Copyright (c) Intel Corporation 1998. * Third-party brands and names are the property of their respective owners.
CONTENTS
Chapter 1
Introduction ......................................................................................................................................... 1-1
1.1 1.2 1.3 1.4 Overview ..................................................................................................................................................... Intel(R) 450NX PCIset Components .............................................................................................................. Intel(R) 450NX PCIset Feature Summary ...................................................................................................... Packaging & Power ..................................................................................................................................... 1-1 1-2 1-3 1-4
Chapter 2
Signal Descriptions ............................................................................................................................ 2-1
2.1 2.2 Conventions ................................................................................................................................................ Summary ..................................................................................................................................................... 2.2.1 Signal Summary, By Component .................................................................................................. 2.2.1.1 MIOC Signal List .......................................................................................................... 2.2.1.2 PXB Signal List ............................................................................................................ 2.2.1.3 RCG Signal List ........................................................................................................... 2.2.1.4 MUX Signal List ........................................................................................................... System Interface ......................................................................................................................................... 2.3.1 System / MIOC Interface ............................................................................................................... 2.3.2 Third-Party Agent / MIOC Interface .............................................................................................. 2-1 2-2 2-2 2-3 2-4 2-5 2-5 2-6 2-6 2-8
2.3
2.4
PCI Interface ............................................................................................................................................... 2-8 2.4.1 Primary Bus .................................................................................................................................. 2-8 2.4.2 64-bit Access Support ................................................................................................................. 2-10 2.4.3 Internal vs. External Arbitration ................................................................................................... 2-10 2.4.4 PIIX4E Interface .......................................................................................................................... 2-11 Memory Subsystem Interface .................................................................................................................... 2.5.1 External Interface ........................................................................................................................ 2.5.2 Internal Interface ......................................................................................................................... 2.5.2.1 RCG / DRAM Interface .............................................................................................. 2.5.2.2 DRAM / MUX Interface .............................................................................................. 2.5.2.3 RCG / MUX Interface ................................................................................................. Expander Interface .................................................................................................................................... Common Support Signals ......................................................................................................................... 2.7.1 JTAG Interface ............................................................................................................................ 2.7.2 Reference Signals ....................................................................................................................... Component-Specific Support Signals ........................................................................................................ 2.8.1 MIOC ........................................................................................................................................... 2.8.2 PXB ............................................................................................................................................ 2.8.3 RCG ............................................................................................................................................ 2.8.4 MUX ............................................................................................................................................ 2-12 2-12 2-14 2-14 2-15 2-15 2-15 2-17 2-17 2-17 2-18 2-18 2-19 2-19 2-19
2.5
2.6 2.7
2.8
Chapter 3
Register Descriptions ......................................................................................................................... 3-1
3.1 3.2 Access Restrictions ..................................................................................................................................... 3-1 I/O Mapped Registers ................................................................................................................................. 3-1 3.2.1 CONFIG_ADDRESS: Configuration Address Register ............................................................... 3-1
Intel(R) 450NX PCIset
-i-
CONTENTS
3.2.2 3.3
CONFIG_DATA: Configuration Data Register .............................................................................. 3-2 3-3 3-4 3-5 3-5 3-6 3-6 3-8 3-9 3-9 3-10 3-11 3-11 3-12 3-12 3-13 3-14 3-15 3-15 3-16 3-16 3-16 3-17 3-17 3-18 3-18 3-18 3-19 3-20 3-20 3-21 3-21 3-21 3-22 3-23 3-24 3-25 3-25 3-25 3-26 3-26 3-27 3-28 3-28 3-29 3-29 3-29 3-31 3-31 3-32 3-32 3-33 3-34 3-35
MIOC Configuration Space .......................................................................................................................... 3.3.1 BUFSIZ: Buffer Sizes ................................................................................................................... 3.3.2 BUSNO[1:0]: Lowest PCI Bus Number, per PXB ......................................................................... 3.3.3 CHKCON: Check Connection ....................................................................................................... 3.3.4 CLASS: Class Code Register ....................................................................................................... 3.3.5 CONFIG: Software-Defined Configuration Register ..................................................................... 3.3.6 CVCR: Configuration Values Captured on Reset ......................................................................... 3.3.7 CVDR: Configuration Values Driven On Reset ............................................................................ 3.3.8 DBC[15:0]: DRAM Bank Configuration Registers ......................................................................... 3.3.9 DEVMAP: System Bus PCI Device Map .................................................................................... 3.3.10 DID: Device Identification Register ............................................................................................. 3.3.11 ECCCMD: ECC Command Register .......................................................................................... 3.3.12 ECCMSK: ECC Mask Register ................................................................................................... 3.3.13 ERRCMD: Error Command Register .......................................................................................... 3.3.14 ERRSTS: Error Status Register ................................................................................................. 3.3.15 GAPEN: Gap Enables ................................................................................................................ 3.3.16 HDR: Header Type Register ....................................................................................................... 3.3.17 HEL[1:0] Host Bus Error Log ...................................................................................................... 3.3.18 HXGB: High Expansion Gap Base ............................................................................................. 3.3.19 HXGT: High Expansion Gap Top ............................................................................................... 3.3.20 IOABASE: I/O APIC Base Address ............................................................................................ 3.3.21 IOAR: I/O APIC Ranges ............................................................................................................. 3.3.22 IOR: I/O Ranges ......................................................................................................................... 3.3.23 ISA: ISA Space ........................................................................................................................... 3.3.24 LXGB: Low Expansion Gap Base ............................................................................................... 3.3.25 LXGT: Low Expansion Gap Top ................................................................................................. 3.3.26 MAR[6:0]: Memory Attribute Region Registers ........................................................................... 3.3.27 MEA[1:0] Memory Error Effective Address ................................................................................. 3.3.28 MEL[1:0] Memory Error Log ....................................................................................................... 3.3.29 MMBASE: Memory-Mapped PCI Base ...................................................................................... 3.3.30 MMR[3:0]: Memory-Mapped PCI Ranges .................................................................................. 3.3.31 PMD[1:0]: Performance Monitoring Data Register ..................................................................... 3.3.32 PME[1:0]: Performance Monitoring Event Selection .................................................................. 3.3.33 PMR[1:0]: Performance Monitoring Response ........................................................................... 3.3.34 RC: Reset Control Register ........................................................................................................ 3.3.35 RCGP: RCGs Present ................................................................................................................ 3.3.36 REFRESH: DRAM Refresh Control Register ............................................................................. 3.3.37 RID: Revision Identification Register .......................................................................................... 3.3.38 ROUTE[1:0]: Route Field Seed ................................................................................................. 3.3.39 SMRAM: SMM RAM Control Register ........................................................................................ 3.3.40 SUBA[1:0]: Bus A Subordinate Bus Number, per PXB .............................................................. 3.3.41 SUBB[1:0]: Bus B Subordinate Bus Number, per PXB .............................................................. 3.3.42 TCAP[0:3]: Target Capacity, per PXB/PCI Port .......................................................................... 3.3.43 TOM: Top of Memory ................................................................................................................. 3.3.44 VID: Vendor Identification Register ............................................................................................ PXB Configuration Space .......................................................................................................................... 3.4.1 BUFSIZ: Buffer Sizes ................................................................................................................. 3.4.2 CLASS: Class Code Register ..................................................................................................... 3.4.3 CLS: Cache Line Size ................................................................................................................ 3.4.4 CONFIG: Configuration Register ................................................................................................ 3.4.5 DID: Device Identification Register ............................................................................................. 3.4.6 ERRCMD: Error Command Register .......................................................................................... 3.4.7 ERRSTS: Error Status Register .................................................................................................
3.4
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Intel(R) 450NX PCIset
CONTENTS
3.4.8 3.4.9 3.4.10 3.4.11 3.4.12 3.4.13 3.4.14 3.4.15 3.4.16 3.4.17 3.4.18 3.4.19 3.4.20 3.4.21 3.4.22 3.4.23 3.4.24 3.4.25 3.4.26 3.4.27 3.4.28 3.4.29 3.4.30 3.4.31 3.4.32 3.4.33 Chapter 4
GAPEN: Gap Enables ................................................................................................................ HDR: Header Type Register ...................................................................................................... HXGB: High Expansion Gap Base ............................................................................................. HXGT: High Expansion Gap Top ............................................................................................... IOABASE: I/O APIC Base Address ............................................................................................ ISA: ISA Space .......................................................................................................................... LXGB: Low Expansion Gap Base .............................................................................................. LXGT: Low Expansion Gap Top ................................................................................................ MAR[6:0]: Memory Attribute Region Registers .......................................................................... MLT: Master Latency Timer Register ......................................................................................... MMBASE: Memory-Mapped PCI Base ..................................................................................... MMT: Memory-Mapped PCI Top ............................................................................................... MTT: Multi-Transaction Timer Register ..................................................................................... PCICMD: PCI Command Register ............................................................................................. PCISTS: PCI Status Register .................................................................................................... PMD[1:0]: Performance Monitoring Data Register ..................................................................... PME[1:0]: Performance Monitoring Event Selection .................................................................. PMR[1:0]: Performance Monitoring Response .......................................................................... RID: Revision Identification Register ......................................................................................... RC: Reset Control Register ....................................................................................................... ROUTE: Route Field Seed ......................................................................................................... SMRAM: SMM RAM Control Register ....................................................................................... TCAP: Target Capacity .............................................................................................................. TMODE: Timer Mode ................................................................................................................. TOM: Top of Memory ................................................................................................................. VID: Vendor Identification Register ............................................................................................
3-36 3-36 3-36 3-36 3-37 3-37 3-37 3-37 3-38 3-38 3-38 3-39 3-39 3-39 3-40 3-41 3-42 3-43 3-44 3-44 3-45 3-45 3-46 3-46 3-47 3-47
System Address Maps ....................................................................................................................... 4-1
4.1 Memory Address Map ................................................................................................................................. 4.1.1 Memory-Mapped I/O Spaces ........................................................................................................ 4.1.2 SMM RAM Support ....................................................................................................................... I/O Space .................................................................................................................................................... PCI Configuration Space ............................................................................................................................. 4-1 4-4 4-4 4-5 4-6
4.2 4.3
Chapter 5
Interfaces ............................................................................................................................................. 5-1
5.1 5.2 5.3 5.4 5.5 System Bus ................................................................................................................................................. PCI Bus ....................................................................................................................................................... Expander Bus .............................................................................................................................................. 5.3.1 Expander Electrical Signal and Clock Distribution ........................................................................ Third-Party Agents ...................................................................................................................................... Connectors .................................................................................................................................................. 5-1 5-1 5-1 5-2 5-2 5-3
Chapter 6
Memory Subsystem ............................................................................................................................ 6-1
6.1 Overview ..................................................................................................................................................... 6.1.1 Physical Organization ................................................................................................................... 6.1.2 Configuration Rules and Limitations ............................................................................................. 6.1.2.1 Interleaving .................................................................................................................. 6.1.2.2 Address Bit Permuting Rules and Limitations ............................................................. 6.1.2.3 Card to Card (C2C) Interleaving Rules and limitations ................................................ 6.1.3 Address Bit Permuting .................................................................................................................. 6-1 6-1 6-3 6-3 6-4 6-4 6-5
Intel(R) 450NX PCIset
-iii-
CONTENTS
6.1.4 6.1.5 Chapter 7
Card to Card (C2C) Interleaving .................................................................................................... 6-5 Memory Initialization ...................................................................................................................... 6-6
Transaction Summary ......................................................................................................................... 7-1
7.1 Host To/From Memory Transactions ........................................................................................................... 7.1.1 Reads and Writes .......................................................................................................................... 7.1.2 Cache Coherency Cycles .............................................................................................................. 7.1.3 Interrupt Acknowledge Cycles ....................................................................................................... 7.1.4 Locked Cycles ............................................................................................................................... 7.1.5 Branch Trace Cycles ..................................................................................................................... 7.1.6 Special Cycles ............................................................................................................................... 7.1.7 System Management Mode Accesses .......................................................................................... 7.1.8 Third-Party Intervention ................................................................................................................. Outbound Transactions ................................................................................................................................ 7.2.1 Supported Outbound Accesses ..................................................................................................... 7.2.2 Outbound Locked Transactions ..................................................................................................... 7.2.3 Outbound Write Combining ........................................................................................................... 7.2.4 Third-Party Intervention on Outbounds ......................................................................................... 7-1 7-1 7-1 7-1 7-1 7-2 7-2 7-3 7-3 7-4 7-4 7-4 7-4 7-4
7.2
7.3
Inbound Transactions .................................................................................................................................. 7-5 7.3.1 Inbound LOCKs ............................................................................................................................. 7-5 7.3.2 South Bridge Accesses ................................................................................................................. 7-5 Configuration Accesses ............................................................................................................................... 7-6
7.4
Chapter 8
Arbitration, Buffers & Concurrency ................................................................................................... 8-1
8.1 8.2 8.3 PCI Arbitration Scheme ............................................................................................................................... 8-1 Host Arbitration Scheme .............................................................................................................................. 8-1 8.2.1 Third Party Arbitration .................................................................................................................... 8-2 South Bridge Support ................................................................................................................................... 8.3.1 I/O Bridge Configuration Example. ................................................................................................ 8.3.2 PHOLD#/PHLDA# Protocol ........................................................................................................... 8.3.3 WSC# Protocol .............................................................................................................................. 8-2 8-2 8-3 8-3
Chapter 9
Data Integrity & Error Handling .......................................................................................................... 9-1
9.1 DRAM Integrity ............................................................................................................................................. 9.1.1 ECC Generation ............................................................................................................................ 9.1.2 ECC Checking and Correction ...................................................................................................... 9.1.3 ECC Error Reporting ..................................................................................................................... 9.1.4 Memory Scrubbing ........................................................................................................................ 9.1.5 Debug/Diagnostic Support ............................................................................................................. 9-1 9-1 9-1 9-1 9-2 9-2
9.2 9.3 9.4
System Bus Integrity .................................................................................................................................... 9-2 9.2.1 System Bus Control & Data Integrity ............................................................................................. 9-3 PCI Integrity ................................................................................................................................................. 9-3 Expander Bus .............................................................................................................................................. 9-3
Chapter 10
System Initialization .......................................................................................................................... 10-1
10.1 Post Reset Initialization .............................................................................................................................. 10.1.1 Reset Configuration Using CVDR/CVCR .................................................................................... 10.1.1.1 Configuration Protocol ................................................................................................ 10.1.1.2 Special Considerations for Third-Party Agents .......................................................... 10-1 10-1 10-1 10-2
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Intel(R) 450NX PCIset
CONTENTS
Chapter 11
Clocking and Reset .......................................................................................................................... 11-1
11.1 11.2 Clocking ..................................................................................................................................................... System Reset ............................................................................................................................................ 11.2.1 Intel(R) 450NX PCIset Reset Structure ......................................................................................... 11.2.2 Output States During Reset ........................................................................................................ 11.2.2.1 MIOC Reset State ..................................................................................................... 11.2.2.2 PXB Reset State ........................................................................................................ 11.2.2.3 RCG Reset State ....................................................................................................... 11.2.2.4 MUX Reset State ....................................................................................................... 11-1 11-2 11-2 11-5 11-6 11-8 11-9 11-9
Chapter 12
Electrical Characteristics ................................................................................................................. 12-1
12.1 Signal Specifications ................................................................................................................................. 12.1.1 Unused Pins ................................................................................................................................ 12.1.2 Signal Groups ............................................................................................................................. 12.1.3 The Power Good Signal: PWRGD .............................................................................................. 12.1.4 LDSTB# Usage ........................................................................................................................... 12.1.5 VCCA Pins .................................................................................................................................. Maximum Ratings ...................................................................................................................................... DC Specifications ...................................................................................................................................... AC Specifications .................................................................................................................................... Source Synchronous Data Transfers ...................................................................................................... I/O Signal Simulations: Ensuring I/O Timings ......................................................................................... Signal Quality Specifications ................................................................................................................... 12.7.1 Intel(R) 450NX PCIset Ringback Specification ............................................................................ 12.7.2 Intel(R) 450NX PCIset Undershoot Specification ........................................................................ 12.7.3 Skew Requirements .................................................................................................................. Intel(R) 450NX PCIset Thermal Specifications .......................................................................................... 12.8.1 Thermal Solution Performance ................................................................................................. 12-1 12-1 12-1 12-3 12-5 12-5 12-6 12-7 12-11 12-20 12-21 12-21 12-21 12-24 12-24 12-25 12-25
12.2 12.3 12.4 12.5 12.6 12.7
12.8 12.9
Mechanical Specifications ....................................................................................................................... 12-26 12.9.1 Pin Lists Sorted by Pin Number: ............................................................................................... 12-26 12.9.2 Pin Lists Sorted by Signal ......................................................................................................... 12-72 12.9.3 Package information ............................................................................................................... 12-118 12.9.3.1 324 BGA Package Information .............................................................................. 12-118 12.9.3.2 540 PBGA Package Information ............................................................................ 12-120
Intel(R) 450NX PCIset
-v-
CONTENTS
-vi-
Intel(R) 450NX PCIset
Introduction
1
1.1
Overview
The Intel(R) 450NX PCIset provides an integrated Host-to-PCI bridge and memory controller optimized for multiprocessor systems and standard high-volume (SHV) servers based on the Pentium(R) II XeonTM processor variant of the P6 family. The Intel 450NX PCIset consists of four components: 82454NX PCI Expander Bridge (PXB), 82451NX Memory and I/O Bridge Controller (MIOC), 82452NX RAS/CAS Generator (RCG), and 82453NX Data Path Multiplexor (MUX). Figure 1-1 illustrates a typical SHV server system based on the Intel 450NX PCIset. The system bus interface supports up to 4 Pentium II Xeon processors at 100 MHz. An additional bus mastering agent such as a cluster bridge can be supported at reduced frequencies. Two dedicated PCI Expander Bridges (PXBs) can be connected via the Expander L2
Cache Pentium(R) II XeonTM processor Optional Cluster Bridge
Cache Pentium II Xeon processor
L2
Cache Pentium II Xeon processor
L2
Cache Pentium II Xeon processor
L2
System Bus
AGTL+ 100 MHz
MA[13:0] Control
Expander Buses
X1
X0
PXB #1
PCI Expander Bridge 1B PCI Slots 1A
PXB #0
PCI Expander Bridge 0B 0A
RCGs
third-party controls
MIOC
Memory and I/O Controller
MD[71:0] MUXs
Memory Subsystem 1 or 2 cards
BMIDE HDDs USB IDE CD-ROM ISA slots
XCVR KBC 8042 SIO
PIIX4E
South Bridge
I/O APIC BIOS Flash EPROM
USB
4 PCI Buses 32-bit, 33 MHz, 3.3v or 5v Can link pairs into 64-bit bus
Figure 1-1:
Simplified Intel(R) 450NX PCIset System Block Diagram
Intel(R) 450NX PCIset
1-1
1. Introduction
Bus. Each PXB provides two independent 32-bit, 33 MHz PCI buses, with an option to link the two buses into a single 64-bit, 33 MHz bus. The Intel 450NX PCIset memory subsystem supports one or two memory cards. Each card is comprised of an RCG, a DRAM array, and two MUXs. The MIOC issues requests to the RCG components on each card to generate RAS#, CAS#, and WE# outputs to the DRAMs. The MUX components provide the datapath for the DRAM arrays. Up to 8 GB of memory in various configurations are supported. Other capabilities of the Intel 450NX PCIset include: * * * Full Pentium(R) II XeonTM processor bus interface (36-bit address, 64-bit data) at 100 MHz. Support for two dedicated PCI expander bridges (PXBs) attached behind the system bus so as not to add additional electrical load to the system bus. Support for both internal and external system bus and I/O bus arbitration.
Supporting Devices
The Intel 450NX PCIset is designed to support the PIIX4E south bridge. The PIIX4E is a highly integrated mulit-functional component that supports the following capabilities: * * * * * PCI Rev 2.1-compliant PCI-to-ISA Bridge with support for 33-MHz PCI operations Enhanced DMA controller 8259 Compatible Programmable Interrupt Controller System Timer functions Integrated IDE controller with Ultra DMA/33 support
1.2
Intel(R) 450NX PCIset Components
MIOC Memory and I/O Bridge Controller The MIOC accepts access requests from the system bus and directs those accesses to memory or one of the PCI buses. The MIOC also accepts inbound requests from the PCI buses. The MIOC provides the data port and buffering for data transferred between the system bus, PXBs and memory. In addition, the MIOC generates the appropriate controls to the RCG and MUX components to control data transfer to and from the memory. PXB PCI Expander Bridge The PXB provides the interface to two independent 32-bit, 33 MHz Rev 2.1-compliant PCI buses. The PXB is both a master and target on each PCI bus. RAS/CAS Generator The RCG is responsible for accepting memory requests from the MIOC and converting these into the specific signals and timings required by the DRAM. Each RCG controls up to four banks of memory. Data Path Multiplexor The MUX provides the multiplexing and staging required to support memory interleaving between the DRAMs and the MIOC. Each MUX provides the data path for one-half of a Qword for each of four interleaves.
RCG
MUX
1-2
Intel(R) 450NX PCIset
1.3 Intel(R) 450NX PCIset Feature Summary
1.3
Intel(R) 450NX PCIset Feature Summary
System Bus Support
* * * * * * * * * *
Fully supports the Pentium(R) II XeonTM processor bus protocol at bus frequencies up to 100 MHz. Functionally and electrically compatible with the original and Pentium II P6 family processor buses. Fully supports 4-way multiprocessing, with performance scaling to 3.5x that of a uniprocessor system. Full 36-bit address decode and drive capability. Full 64-bit data bus (32-bit data bus mode is not supported). Parity protection on address and control signals, ECC protection on data signals. 8-deep in-order queue; 24-deep memory request queue; 2-deep outbound read-request queue per PCI bus; 6-deep outbound write-posting queue per PCI bus. AGTL+ bus driver technology. Intel(R) 450NX PCIset adds only one load to the system bus. Intel 450GX PCIset-compatible third-party request/grant and control signals, allowing cluster bridges to be placed on the system bus.
DRAM Interface Support
* * * * * * * *
Memory technologies supported are 16- and 64-Mbit, 60nsec and 50nsec 3.3v EDO DRAM devices. Supports from 32 MB to 8 GB of memory, in 64 MB increments after the initial 32 MB. Supports 4-way interleaved operation, with 2-way interleave supported in the first bank of card 0 to permit entry-level systems with minimal memory. Supports memory address bit permuting (ABP) to obtain alternate row selection bits. Supports card-to-card interleaving to further distribute memory accesses across multiple banks of memory. Staggered CAS-before-RAS refresh. ECC with single-bit error correction and scrub-on-error in the memory. Extensive Host-to-Memory and PCI-to-Memory write data buffering.
I/O Bridge Support
*
Up to four independent 32-bit PCI ports (using two PXBs) - each supports up to 10 electrical loads (connectors count as loads). - each provides internal arbitration for up to 6 masters plus a south bridge on the compatibility PCI bus, or external arbitration. Synchronous operation to the system bus clock using a 3:1 system bus/PCI bus gearing ratio. - 3:1 ratio supports a 100 MHz system bus and 33.33 MHz PCI bus. - 3:1 ratio supports a 90 MHz system bus and 30 MHz PCI bus (or lower, depending on effect of 6th load). Parity protection on all PCI signals. Inbound read prefetches of up to 4 cache lines. Outbound write assembly of full/partial line writes. Data streaming support from PCI to DRAM.
*
* * * *
Intel(R) 450NX PCIset
1-3
1. Introduction
System Management Features
*
Provides controlled access to the Intel Architecture System Management Mode (SMM) memory space (SM RAM).
Test & Tuning Features
* *
Signal interconnectivity testing via boundary scan. Access to internal control and status registers via JTAG TAP port. I2C access is not provided in the PCIset; however, error indicators are reported to pins which can be monitored and sampled using I2C capabilities if provided elsewhere in the system. System bus, memory and I/O performance counters with programmable events.
*
Reliability/Availability/Serviceability (RAS) Features
* * *
ECC coverage of system data bus and memory; parity coverage of system bus controls, PCI bus, and Expander bus. ECC bits can be corrupted via selective masking for diagnostics. Fault recording of the first two ECC errors. Each includes error type and syndrome. Memory ECC error logs include the effective address, allowing identification of the failing location. Error logs are not affected by reset, allowing recovery software to examine the logs.
1.4
Packaging & Power
* Table 1-1 indicates the signal count, package and power for each component in the Intel(R) 450NX PCIset. In a common high-end configuration, using two memory cards (each with one RCG and two MUX components), two PXBs and 3.3 V supplies, the Intel 450NX PCIset would contribute approximately 47 watts.
Table 1-1: Signals, Pins, Packaging and Power Chip MIOC PXB RCG MUX Signals 348 177 173 207 Package PLGA-5402 PLGA-540 BGA-324 BGA-324
2
Footprint 42.5 mm 42.5 mm 27.0 mm 27.0 mm
Power1 13.2 W 7.8 W 2.5 W 3.3 W
Notes: 1. Assumes 3.3 V supplies. 2. Requires heat sink.
1-4
Intel(R) 450NX PCIset
Signal Descriptions
2
This chapter provides a detailed description of all signals used in any component in the Intel(R) 450NX PCIset.
2.1
Conventions
The terms assertion and deassertion are used extensively when describing signals, to avoid confusion when working with a mix of active-high and active-low signals. The term assert, or assertion, indicates that the signal is active, independent of whether the active level is represented by a high or low voltage. The term deassert, or deassertion, indicates that the signal is inactive. The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when at the high voltage level. When discussing data values used inside the chip set, the logical value is used; i.e., a data value described as "1101b" would appear as "1101b" on an active-high bus, and as "0010b" on an active-low bus. When discussing the assertion of a value on the actual pin, the physical value is used; i.e., asserting an active-low signal produces a "0" value on the pin. The following notations are used to describe the signal type: I O I/O OD Input pin Output pin Bidirectional (input/output) pin Open drain output pin (other than AGTL+ signals)
The signal description also includes the type of buffer used for the particular signal: AGTL+ PCI LVTTL 2.5V Analog Open drain AGTL+ interface. PCI-compliant 3.3 V/5 V-tolerant interface Low-voltage (3.3 V) TTL-compatible signals. 2.5 V CMOS signals. Typically a voltage reference or specialty power supply.
Intel(R) 450NX PCIset
2-1
2. Signal Descriptions
Some signals or groups of signals have multiple versions. These signal groups may represent distinct but similar ports or interfaces, or may represent identical copies of the signal used to reduce loading effects. The following conventions are used: RR(A,B,C)XX RR(A,...,D)XX RRpXX, where p=A,B,C expands to: RRAXX, RRBXX, and RRCXX expands to: RRAXX, RRBXX, RRCXX, and RRDXX expands to: RRAXX, RRBXX, and RRCXX
Typically, upper case groups (e.g., "(A,B,C)") represent functionally similar but logically distinct signals; each signal provides an independent control, and may or may not be asserted at the same time as the other signals in the grouping. In contrast, lower case groups (e.g., "(a,b,c)") typically represent identical duplicates of a common signal provided to reduce loading.
2.2
Summary
Figure 2-1 illustrates the partitioning of interfaces across the components in the Intel(R) 450NX PCIset. The remainder of this section lists the signals and signal counts in each interface by component. The signal functions are described in subsequent sections.
Pentium (R) II XeonTM processor bus System Interface
MIOC
Memory Interface (External)
MUXs RCG
Expander Interface (2)
1
0
DRAM Array
memory cards
Memory Interface (Internal)
PXB #1
1B 1A
PXB #0
0B 0A PCI Bus #0A is the Compatibility Bus
PCI Interfaces (2)
PCI Interfaces (2)
Figure 2-1:
Interface Summary: Partitioning
2.2.1
Signal Summary, By Component
The following tables provide summary lists of all signals in each component, sorted alphabetically within interface type. The signals are described in a later section.
2-2
Intel(R) 450NX PCIset
2.2 Summary
2.2.1.1
MIOC Signal List System Interface A[35:3]# AGTL+ I/O ADS# AGTL+ I/O AERR# AGTL+ I/O AP[1:0]# AGTL+ I/O BERR# AGTL+ I/O BINIT# AGTL+ I/O BNR# AGTL+ I/O BP[1:0]# LVTTL I/OD BPRI# AGTL+ I/O BREQ[0]# AGTL+ O D[63:0]# AGTL+ I/O DBSY# AGTL+ I/O DEFER# AGTL+ I/O Third-Party Agent Interface IOGNT# LVTTL I IOREQ# LVTTL O Memory Subsystem / External Interface BANK[2:0]# AGTL+ O CARD[1:0]# AGTL+ O CMND[1:0]# AGTL+ O CSTB# AGTL+ O DCMPLT(a,b)# AGTL+ I/O DOFF[1:0]# AGTL+ O DSEL[1:0]# AGTL+ O DSTBN[3:0]# AGTL+ I/O DSTBP[3:0]# AGTL+ I/O Expander Interface (two per MIOC: 0,1) X(0,1)ADS# AGTL+ I/O X(0,1)BE[1:0]# AGTL+ I/O X(0,1)BLK# AGTL+ O X(0,1)CLK CMOS O X(0,1)CLKB CMOS O X(0,1)CLKFB CMOS I X(0,1)D[15:0]# AGTL+ I/O X(0,1)HRTS# AGTL+ O X(0,1)HSTBN# AGTL+ O Common Support Signals CRES[1:0] Analog I TCK 2.5V I TDI 2.5V I TDO 2.5V OD 134 I/O I/O I I OD I I/O I/O I/O I/O I/O
DEP[7:0]# DRDY# HIT# HITM# INIT# LOCK# REQ[4:0]# RP# RS[2:0]# RSP# TRDY#
AGTL+ AGTL+ AGTL+ AGTL+ 2.5V AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
4 TPCTL[1:0] LVTTL I 119 DVALID(a,b)# MA[13:0]# MD[71:0]# MRESET# PHIT(a,b)# ROW# RCMPLT(a,b)# RHIT(a,b)# WDEVT# X(0,1)HSTBP# X(0,1)PAR# X(0,1)RST# X(0,1)RSTB# X(0,1)RSTFB# X(0,1)XRTS# X(0,1)XSTBN# X(0,1)XSTBP# AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ O O I/O O I O I I O 2 x 33 O I/O O O I I I I 16 TMS TRST# VCCA (3) VREF (6) 2.5V 2.5V Analog Analog I I I I
Intel(R) 450NX PCIset
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2. Signal Descriptions
Component-Specific Support Signals LVTTL O CRESET# LVTTL I/OD ERR[1:0]# 2.5V I HCLKIN LVTTL O INTREQ# TOTAL SIGNALS
PWRGD PWRGDB RESET# SMIACT#
LVTTL LVTTL AGTL+ LVTTL
9 I O I/O O 348
2.2.1.2
PXB Signal List PCI Bus Interface (2 per PXB: A,B) PCI I/O P(A,B)AD[31:0] P(A,B)PAR PCI I/O P(A,B)C/BE[3:0]# P(A,B)PERR# LVTTL I P(A,B)CLKFB P(A,B)REQ[5:0]# LVTTL O P(A,B)CLK P(A,B)RST# PCI I/O P(A,B)DEVSEL# P(A,B)SERR# PCI I/O P(A,B)FRAME# P(A,B)STOP# PCI O P(A,B)GNT[5:0]# P(A,B)TRDY# PCI I/O P(A,B)IRDY# P(A,B)XARB# PCI I/O P(A,B)LOCK# PCI Bus Interface / Non-Duplicated (one set per PXB) PCI I/O ACK64# PHLDA# PCI I MODE64# REQ64# PCI I PHOLD# WSC# Expander Interface (one per PXB) XADS# AGTL+ I/O XHSTBP# XBE[1:0]# AGTL+ I/O XIB XBLK# AGTL+ I XPAR# XCLK CMOS I XRST# XD[15:0]# AGTL+ I/O XXRTS# XHRTS# AGTL+ I XXSTBN# XHSTBN# AGTL+ I XXSTBP# Common Support Signals Analog I CRES[1:0] TMS 2.5V I TCK TRST# 2.5V I TDI VCCA (3) 2.5V OD TDO VREF (2) Component-Specific Support Signals PCI OD INTRQ(A,B)# PIIXOK# LVTTL I/OD PWRGD P(A,B)MON[1:0]# TOTAL SIGNALS 2 x 61 I/O I/O I O OD I/O I/O I 6 PCI PCI PCI AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ O I/O O 30 I O I/O I O O O 12 2.5V I 2.5V I Analog I Analog I 8 LVTTL I LVTTL I 177
PCI PCI PCI PCI PCI PCI PCI PCI
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Intel(R) 450NX PCIset
2.2 Summary
2.2.1.3
RCG Signal List Memory Subsystem / External Interface BANK[2:0]# AGTL+ I CARD# AGTL+ I CMND[1:0]# AGTL+ I CSTB# AGTL+ I GRCMPLT# AGTL+ I/O MA[13:0]# AGTL+ I Memory Subsystem / Internal Interface ADDR(A,B,C,D)[13:0] LVTTL O AVWP# AGTL+ O CAS(A,B,C,D)(a,b,c,d)[1:0]# LVTTL O LDSTB# AGTL+ O Common Support Signals CRES[1:0] Analog I TCK 2.5V I TDI 2.5V I TDO 2.5V OD Component-Specific Support Signals BANKID# LVTTL I DR50H# LVTTL I TOTAL SIGNALS 27 MRESET# PHIT# RCMPLT# RHIT# ROW# AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ I O O O I 123 LRD# RAS(A,B,C,D)(a,b,c,d)[1:0]# WDME# WE(A,B,C,D)(a,b)# TMS TRST# VCCA VREF (2) DR50T# HCLKIN AGTL+ LVTTL AGTL+ LVTTL 2.5 V 2.5 V Analog Analog O O O O 10 I I I I 4 LVTTL I 2.5 V I 173
2.2.1.4
MUX Signal List Memory Subsystem / External Interface DCMPLT# AGTL+ I/O DOFF[1:0]# AGTL+ I DSEL# AGTL+ I DSTBP[1:0]# AGTL+ I/O DSTBN[1:0]# AGTL+ I/O Memory Subsystem / Internal Interface AVWP# AGTL+ I LDSTB# AGTL+ I LRD# AGTL+ I Q0D[35:0] LVTTL I/O Common Support Signals CRES[1:0] Analog I TCK 2.5 V I TDI 2.5 V I TDO 2.5 V OD Component-Specific Support Signals HCLKIN 2.5 V I TOTAL SIGNALS 48 DVALID# GDCMPLT# MD[35:0]# MRESET# WDEVT# Q1D[35:0] Q2D[35:0] Q3D[35:0] WDME# TMS TRST# VCCA VREF (2) AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ LVTTL LVTTL LVTTL AGTL+ 2.5 V 2.5 V Analog Analog I I/O I/O I I 148 I/O I/O I/O I 10 I I I I 1 207
Intel(R) 450NX PCIset
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2. Signal Descriptions
2.3
System Interface
The MIOC provides the Intel(R) 450NX PCIset's sole connection to the system bus. This section describes the Intel 450NX PCIset-specific uses of these signals.
2.3.1
System / MIOC Interface
A[35:3]# Address Bus AGTL+ I/O A[35:3]# connect to the system address bus. During processor cycles the A[35:3]# are inputs. The MIOC drives A[35:3]# during snoop cycles on behalf of PCI initiators. The address bus is inverted on the system bus. Address Strobe AGTL+ I/O The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. Address Parity Error AGTL+ I/O AERR# is asserted by any agent that detects an address parity error. Address Parity AGTL+ I/O Parity protection on the address bus. AP#[1] covers A#[35:24], and AP#[0] covers A#[23:3]. They are valid on both cycles of the request. Bus Error AGTL+ I/O This signal is asserted by any agent that observes an unrecoverable bus protocol violation. Bus Initialization AGTL+ I/O BINIT# is asserted to re-initialize the bus state machines. The MIOC will terminate any ongoing PCI transaction and reset its inbound and outbound queues. No configuration registers or error logging registers are affected. Block Next Request AGTL+ I/O Used to block the current request bus owner from issuing a new request. Performance Monitoring LVTTL I/OD In normal operation, the MIOC can be configured to drive performance monitoring data out of either of these pins, similar in function to the BP pins provided on the processors. Priority Agent Bus Request AGTL+ O The MIOC is the only Priority Agent on the system bus. It asserts this signal to obtain ownership of the address bus. BPRI# has priority over symmetric bus requests. Symmetric Agent Bus Request AGTL+ O This signal is asserted by the MIOC when RESET# is asserted, to select the boot processor. It is deasserted 2 host clocks after RESET# is deasserted.
ADS#
AERR#
AP[1:0]#
BERR#
BINIT#
BNR#
BP[1:0]#
BPRI#
BREQ[0]#
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Intel(R) 450NX PCIset
2.3 System Interface
D[63:0]#
Data AGTL+ I/O These signals are connected to the system data bus. The data signals are inverted on the system bus. Data Bus Busy AGTL+ I/O Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Data Bus ECC/Parity AGTL+ I/O These signals provide parity or ECC for the D#[63:0] signals. The MIOC only provides ECC. Defer AGTL+ I/O DEFER# is driven by the addressed agent to indicate that the transaction cannot be guaranteed to be globally observed. Data Ready Asserted for each cycle that valid data is transferred. AGTL+ I/O
DBSY#
DEP[7:0]#
DEFER#
DRDY#
HIT#
Hit AGTL+ I The MIOC never asserts HIT#; it has no cache, and never snoop stalls. Hit Modified AGTL+ I The MIOC never asserts HITM#; it has no cache, and never snoop stalls. Soft Reset 2.5V OD INIT# may be asserted to request a soft reset of the processors. During a system hard reset, the INIT# signal may be optionally asserted to cause the processors to initiate their BIST. The INIT# signal is not asserted during power-good reset. Lock AGTL+ I All system bus cycles sampled with the assertion of LOCK# and ADS#, until the negation of LOCK#, must be atomic; i.e., no PCI activity to DRAM is allowed and the locked cycle must be translated to PCI if targeted for the PCI bus. Request Command AGTL+ I/O Asserted during both clocks of a request phase. In the first clock, the signals define the transaction type to a level which is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type. Request Parity AGTL+ I/O Even parity protection on ADS# and REQ[4:0]#. It is valid on both cycles of the request. Response Signals Indicate response type as shown below: 000 Idle state 100 Hard failure 001 Retry 101 No Data 010 Deferred 110 Implicit writeback 011 reserved 111 Normal Data AGTL+ I/O
HITM#
INIT#
LOCK#
REQ[4:0]#
RP#
RS[2:0]#
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2. Signal Descriptions
RSP#
Response Parity Signal Parity protection on RS[2:0]#.
AGTL+ I/O
TRDY#
Target Ready AGTL+ I/O Indicates that the target of the system transaction is able to enter the data transfer phase.
2.3.2
Third-Party Agent / MIOC Interface
The following signals provide support for an additional non-processor, third-party agent (TPA) on the system bus. Such agents may need priority access to the system bus itself, or may need to intervene in transactions between the processors and the Intel(R) 450NX PCIset. IOGNT# I/O Grant LVTTL I The IOGNT# signal has two modes: Internal Arbitration Mode and External Arbitration Mode, selected by a bit in the MIOC's CONFIG register. In Internal Arbitration Mode IOGNT# is an input from another bridge device which is requesting ownership of the BPRI# signal. In external arbitration mode, this bridge requests BPRI# ownership from an external bridge arbiter. IOGNT# should be asserted by the external arbiter when this MIOC has been granted ownership of the BPRI# signal. I/O Request LVTTL O The IOREQ# signal has two modes: Internal Arbitration Mode and External Arbitration Mode, selected by a bit in the MIOC's CONFIG register. In Internal Arbitration Mode IOREQ# is the grant to another bridge device that is making a request for ownership of the BPRI# signal. In external arbitration mode this signal is asserted to request ownership of the BPRI# signal. Third Party Control LVTTL I These signals allow an agent participating in transactions between the Intel(R) 450NX PCIset and another bus agent as a "third-party" to control the responses generated by the Intel 450NX PCIset. 00 Accept The MIOC will accept the request and provide the normal response. 01 reserved - 10 Retry The MIOC will generate a RETRY response. 11 Defer The MIOC will generate a DEFERRED response.
IOREQ#
TPCTL[1:0]
2.4
2.4.1
PCI Interface
Primary Bus
There are two primary PCI buses per PXB, identified as the "a" bus and the "b" bus groups. Each signal name includes a "p", indicating the PCI bus port; p = A or B.
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Intel(R) 450NX PCIset
2.4 PCI Interface
PpAD[31:0]
PCI Address/Data PCI I/O PCI Address and Data signals are multiplexed on this bus. The physical byte address is output during the address phase and the data follows in the subsequent data phase(s). Command/Byte Enable PCI I/O PCI Bus Command and Byte Enable signals are multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as byte enables. PCI Clock LVTTL O This signal is an output with a derived frequency equal to 1/3 of the system bus frequency. PCI Clock Feedback LVTTL I This signal is connected to the output of a low skew PCI clock buffer tree. It is used to synchronize the PCI clock driven from PpCLK to the clock used for the internal PCI logic. Device Select PCI I/ O DEVSEL# is driven by the device that has decoded its address as the target of the current access. Frame PCI I/O The PXB asserts FRAME# to indicate the start of a bus transaction. While FRAME# is asserted, data transfers continue. When FRAME# is negated, the transaction is in the final data phase. FRAME# is an input when the PXB acts as a PCI target. Initiator Ready PCI I/O This signal is asserted by a master to indicate its ability to complete the current data transfer. IRDY# is an output when the PXB acts as a PCI initiator and an input when the PXB acts as a PCI target. Parity PCI I/O PAR is driven by the PXB when it acts as a PCI initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the PXB when it acts as a PCI target during each data phase of a PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#. PCI Reset PCI O PCI Bus Reset forces the PCI interfaces of each device to a known state. The PXB generates a minimum 1 ms pulse on RST#. PCI Parity Error PCI I/O Pulsed by an agent receiving data with bad parity one clock after PAR is asserted. The PXB will generate PERR# active if it detects a parity error on the PCI bus and the PERR# Enable bit in the PCICMD register is set. Lock PCI I/O LOCK# indicates an exclusive bus operation and may require multiple transactions to complete. It is possible for different agents to use the PCI Bus while a single initiator retains ownership of the LOCK# signal.
PpC/BE[3:0]#
PpCLK
PpCLKFB
PpDEVSEL#
PpFRAME#
PpIRDY#
PpPAR
PpRST#
PpPERR#
PpLOCK#
Intel(R) 450NX PCIset
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2. Signal Descriptions
PpTRDY#
Target Ready PCI I/O The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the transaction. TRDY# is an input when the PXB acts as a PCI master and an output when the PXB acts as a PCI target. System Error The PXB asserts this signal to indicate an error condition. PCI OD
PpSERR#
PpSTOP#
Stop PCI I/O STOP# is used for disconnect, retry, and abort sequences on the PCI Bus. It is an input when the PXB acts as a PCI initiator and an output when the PXB acts as a PCI target.
2.4.2
64-bit Access Support
These signals are used only in 64-bit bus mode. There is one set per PXB. ACK64# 64-bit Access Acknowledge PCI I/O This signal is driven by the accessed target to indicate its willingness to transfer 64-bit data. When the PXB is the bus target, this signal is an output. If asserted, the PXB will transfer 64-bit data; otherwise, the PXB will transfer 32-bit data. When the PXB is the bus master, this signal is an input. 64-bit Bus Mode PCI I A strapping pin that selects whether the pair of 32-bit PCI buses are used as two independent 32-bit buses, or linked together as a single 64-bit bus. If asserted, the buses are used as a single 64-bit bus: the 32-bit data bus of the PCI "B" port becomes the high Dword of the 64-bit bus. An internal pull-up insures that the pin appears deasserted if left unconnected. 64-bit Access Request PCI I/O This signal is driven by the bus master to indicate it's desire to transfer 64-bit data. When the PXB is the bus master, this signal is an output. The PXB will assert this signal if it can transfer 64-bit data. When the PXB is the bus target, this signal is an input.
MODE64#
REQ64#
The following 64-bit extension signals are mapped from the existing "B" port signals: AD[63:32] from PBAD[31:0] C/BE[7:4] from PBC/BE[3:0] PAR64 from PBPAR All other controls and status signals in 64-bit operation are taken from the Bus "A" signal set. Unused pins on the "B" side should be tied inactive.
2.4.3
Internal vs. External Arbitration
Each PXB supports both internal arbitration and external arbitration, independently for each PCI bus. While in internal arbitration mode, six pairs of request/grant signals are used to support up to six PCI masters on the bus (plus the PXB itself, and the PIIX4E south bridge on
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Intel(R) 450NX PCIset
2.4 PCI Interface
the compatibility PCI bus). While in external arbitration mode, only one pair (#0) are used, and have different meanings. Each signal name includes a "p", indicating the PCI bus port; p = A or B. PpXARB# External Arbitration Mode PCI I A strapping pin, sampled at the trailing edge of reset. If asserted, the PCI bus is controlled using an external arbiter. If deasserted, the PCI bus is controlled using the PXB's internal arbiter. An internal pull-up insures that the pin appears deasserted if left unconnected.
Internal Arbitration Mode (per PCI bus, p=A,B)
PpREQ[5:0]#
PCI Bus Request PCI I Six independent PCI bus request signals used by the internal PCI arbiter for PCI initiator arbitration. Unused signals should be strapped inactive. PCI Grant PCI O Six independent PCI bus grant signals used by the internal PCI arbiter for PCI initiator arbitration.
PpGNT[5:0]#
External Arbitration Mode (per PCI bus, p=A,B)
When operating in external arbitration mode, REQ[5:1]# and GNT[5:1]# signals are not used. The REQ[0]# signal is redefined as HGNT#, and the GNT[0]# signal is redefined as HREQ#. PpHREQ# Host Request PCI O Generated by the PXB to the external PCI arbiter to request control of the PCI bus to perform a Host-PCI access. Host Grant PCI I Generated by the external PCI arbiter to grant the PCI bus to the PXB to perform a Host-PCI transfer.
PpHGNT#
2.4.4
PIIX4E Interface
The compatibility PCI bus (PCI Bus 0A) supports a PIIX4E south bridge, and requires several additional handshake signals, provided by the PXB. They are active only for Bus 0A.
NOTE These signals, and the associated PHOLDA# and WSC# protocols, cannot be used with the PXB in external arbiter mode.
PHOLD#
PCI Hold This signal is the PIIX4E's request for the PCI bus.
PCI I
PHLDA#
PCI Hold Acknowledge PCI O This signal is driven by the PXB to grant PCI bus ownership to the PIIX4E.
Intel(R) 450NX PCIset
2-11
2. Signal Descriptions
WSC#
Write Snoop Complete PCI O This signal is asserted active to indicate completion of snoop activity on the system bus on the behalf of the last PCI-DRAM write transaction, and that it is safe to send the APIC interrupt message.
2.5
Memory Subsystem Interface
The memory subsystem is comprised of the DRAM arrays and the associated RCGs and MUXs. There is the external interface (between the MIOC and the memory subsystem), and the internal interface (between the various parts of the memory subsystem.)
2.5.1
External Interface
BANK[2:0]# Bank Selects AGTL+ MIOC RCG These signals indicate which memory bank will service this access. BANK[2:0]# are connected to all RCGs on both memory cards. Card Selects AGTL+ MIOC RCG These signals indicate which memory card will service this access. Valid patterns in the Intel(R) 450NX PCIset are 01b=card0 and 10b=card1, allowing CARD[0]# to be connected only to card 0 and CARD[1]# to be connected only to card 1. Each CARD signal is connected to all RCGs on the given memory card. Access Command AGTL+ MIOC RCG These signals encode the command of the current operation. CMND[1:0]# are connected to all RCGs on both memory cards. Command Strobe AGTL+ MIOC RCG This strobe, when activated, indicates the initiation of an access. This signal is connected to all RCGs on both memory cards. Memory Address bus AGTL+ MIOC RCG These signals define the address of the location to be accessed in the DRAM., and are driven on two successive clock cycles to provide up to 28 bits of effective memory address. The signals are connected to all RCGs on both memory cards. Row Selects AGTL+ MIOC RCG These signals indicate which row in the selected memory bank will service this access. These signals are connected to all RCGs on both memory cards. Global RCMPLT# AGTL+, I/O, all RCGs A "global" version of the RCMPLT(a,b)# signals, asserted coincident with RCMPLT#, and by the same agent. Whereas each RCMPLT# signal connects the RCGs on one card with the MIOC, the GRCMPLT# signal connects the
CARD[1:0]#
CMND[1:0]#
CSTB#
MA[13:0]#
ROW#
GRCMPLT#
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2.5 Memory Subsystem Interface
RCGs across both cards while excluding the MIOC. This allows all RCGs to monitor each request completion without placing undue loading on the RCMPLT# signals. MRESET# Memory Subsystem Reset AGTL+ MIOC RCG/MUX This signal represents a hard reset of the memory subsystem. It is asserted following PWRGD or upon the MIOC issuing a processor RESET due to software invocation.
RCMPLTa# RCMPLTb#
Request Complete AGTL+ RCG MIOC This signal, which is driven by the currently active RCG, indicates the completion of a request into the memory array. Typically the "a" signal connects the MIOC and all RCGs on Card #0, while the "b" signal connects the MIOC and all RCGs on Card #1.
PHIT(a,b)# RHIT(a,b)#
Page and Row Hit Status AGTL+ RCG MIOC These signals indicate what resource, if any, delayed the initiation of a read. Typically the "a" signal connects the MIOC and all RCGs on Card #0, while the "b" signal connects the MIOC and all RCGs on Card #1.
DSTBP[3:0]# DSTBN[3:0]#
Data Strobes AGTL+ MUX MIOC This set of four signal-pairs are strobes which qualify the data transferred between the MUX and MIOC. Each strobe pair qualifies 18 bits (two bytes and two check bits), as follows: DSTB[0]# qualifies MD[17:00]#. DSTB[2]# qualifies MD[53:36]#. DSTB[1]# qualifies MD[35:18]#. DSTB[3]# qualifies MD[71:54]#. In a 4:1 interleaved system, with 2 MUXs per card, DSTB[1:0]# strobes the low MUX and DSTB[3:2]# strobes the high MUX. In a 2:1 interleaved system, with only a single MUX per card, DSTB[1:0]# strobes the MUX, and DSTB[3:2]# is not used.
MD[71:36]# MD[35:00]#
Memory Data AGTL+ MUX MIOC These signals are connected to the external datapath of the MUXs. Each MUX provides 36 bits of the 72-bit datapath to the MIOC. AGTL+ MUX MIOC/MUX Data Transfer Complete MIOC MUXs This signal is driven by the source of the data transfer: the MIOC for writes, and the MUX for reads. DCMPLT# active indicates that the data transfer is complete. Typically the "a" signal connects the MIOC and all MUXs on Card #0, while the "b" signal connects the MIOC and all MUXs on Card #1. Data Offset AGTL+ MIOC MUX These two bits, when qualified by the DVALID# signal, define the initial Qword access order for the data transfer. The result is that the critical chunk is accessed first and the remaining chunks are accessed in Intel "Toggle" order.
DCMPLTa# DCMPLTb#
DOFF[1:0]#
Intel(R) 450NX PCIset
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2. Signal Descriptions
DSEL#
Data Card Select AGTL+ MIOC MUX This signal, when qualified by the DVALID# signal, selects which card the memory transfer is coming from or destined towards. Each memory card uses a single DSEL# input, sent to each MUX on the card. The MIOC provides two DSEL# outputs (DSEL[1:0]#), one sent to each card.
DVALIDa# DVALIDb#
Data Transfer Complete AGTL+ MIOC MUX This signal indicates that the DSEL[1:0]#, DOFF[1:0]#, and WDEVT# signals are valid. Typically the "a" signal connects the MIOC and all MUXs on Card #0, while the "b" signal connects the MIOC and all MUXs on Card #1. Global DCMPLT# AGTL+, I/O, all MUXs A "global" version of the DCMPLT(a,b)# signals, asserted coincident with DCMPLT#, and by the same agent. Whereas each DCMPLT# signal connects the MUXs on one card with the MIOC, the GDCMPLT# signal connects the MUXs across both cards while excluding the MIOC. This allows all MUXs to monitor each data completion without placing undue loading on the DCMPLT# signals. Write Data Event AGTL+ MIOC MUX This signal, when qualified by the DVALID# signal, indicates the type of data transfer command. If asserted, the command represents a write data transfer. If deasserted, the command represents a read data transfer.
GDCMPLT#
WDEVT#
2.5.2
2.5.2.1
Internal Interface
RCG / DRAM Interface Each RCG provides four sets of signals to drive four banks in the DRAM array. In each of the following signal names, the "" indicates a set of signals per bank. Each RCG controls four banks; therefore = A, B, C or D. CAS(a,b,c,d)[1:0]# Column Address Strobes LVTTL RCG DRAM These signals are used to latch the column address into the DRAMs. The "a", "b", "c" and "d" versions are duplicates for load reduction. ADDR[13:0] DRAM Address LVTTL RCG DRAM ADDR is used to provide the multiplexed row and column address to DRAM.
RAS(a,b,c,d)[1:0]# Row Address Strobe LVTTL RCG DRAM The RAS signals are used to latch the row address into the DRAMs. Each signal is used to select one DRAM row. The 1:0 signals indicate which row within the bank. The "a", "b", "c" and "d" versions are duplicates for load reduction. WE(a,b)# Write Enable Signal LVTTL RCG DRAM WE# is asserted during writes to main memory. The "a" and "b" versions are duplicates for load reduction.
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Intel(R) 450NX PCIset
2.6 Expander Interface
2.5.2.2
DRAM / MUX Interface Q0D[35:0] Memory Data, Interleave 0 LVTTL DRAM MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave zero. Memory Data, Interleave 1 LVTTL DRAM MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave one. Memory Data, Interleave 2 LVTTL DRAM MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave two. Memory Data, Interleave 3 LVTTL DRAM MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave three.
Q1D[35:0]
Q2D[35:0]
Q3D[35:0]
2.5.2.3
RCG / MUX Interface AVWP# Advance MUX Write Path Pointers AGTL+ RCG MUX This signal is activated by an RCG after performing a memory write. Load Data Strobe AGTL+ RCG MUX This signal controls when read data is latched from the DRAM data bus. Load Read Data AGTL+ RCG MUX This signal indicates when read data is ready to load from the DRAMs. Write Data to Memory Enable AGTL+ RCG MUX This signal enables the MUXes to drive write data to the DRAMs.
LDSTB#
LRD#
WDME#
2.6
Expander Interface
The MIOC component has two Expander interfaces, one for each of the two PXBs supported by Intel(R) 450NX PCIset. These two high speed, low latency interfaces are identified as the X0 bus and the X1 bus groups. Each signal name includes a "p", indicating the Expander port. On the MIOC, p = 0 or 1, designating one of the two interfaces. On the PXB, p is not used. XpADS# Address / Data Strobe. AGTL+ MIOC PXB Bidirectional signal asserted by the sending agent during data transmission. Byte Enables. AGTL+ MIOC PXB Bidirectional signals indicating valid bytes during the data phases of a transmission.
XpBE[1:0]#
Intel(R) 450NX PCIset
2-15
2. Signal Descriptions
XpD[15:0]#
Datapath AGTL+ MIOC PXB This bidirectional datapath is used to transfer addresses and data between the MIOC and the PCI Expander. Host Request to Send. AGTL+ MIOC PXB Request to use the bidirectional Expander bus sent from MIOC to PXB, synchronous to HCLKIN.
XpHRTS#
XpHSTBP# XpHSTBN#
Host Strobes AGTL+ MIOC PXB This pair of opposite-phase strobes are used by the PXB to latch and synchronize incoming data. Bus Parity. AGTL+ MIOC PXB Bidirectional signal indicating even parity across XD[15:0] and XBE[1:0]. Expander Request to Send. AGTL+ PXB MIOC Request to use the bidirectional Expander bus sent from PXB to MIOC, synchronous to HCLKIN.
XpPAR#
XpXRTS#
XpXSTBP# XpXSTBN#
Expander Strobes AGTL+ PXB MIOC This pair of opposite-phase strobes are used by the MIOC to latch and synchronize incoming data.
Support Signals
XpBLK
Block Counters. AGTL+ MIOC PXB This signal is asserted when the Performance Counter Master Enable bit in the MIOC's CONFIG register is set, and is used to affect a nearly simultaneous stop/start of the performance counters across both the MIOC and all PXBs. Host Clock. CMOS MIOC PXB This is the primary clock source provided to the PXB, analogous to HCLKIN for the MIOC, RCG and MUX. Inside the PXB, it is divided by 3 to produce a PCI clock output at 33.33 MHz from an HCLKIN of 100 MHz. Host Clock, 2nd Version. CMOS MIOC ext This is a duplicate of the XpCLK signal, to be used in maintaining PLL synchronization in the MIOC. See XpCLKFB below. Host Clock, Feedback. CMOS ext MIOC This signal is a length-matched copy of the XpCLK signal sent to the PXB, used to maintain PLL synchronization in the MIOC. The XpCLKB signal is length-matched to the XpCLK's path to the PXB, then returned to the MIOC as the XpCLKFB input. Driving Inbound. AGTL+ PXB ext This active-high signal is asserted when the PXB is driving data over the Expander bus. This pin is not connected to the MIOC. PXB Reset. AGTL+ MIOC PXB This signal issues a hard reset of the PXB, including the dependent PCI buses.
XpCLK
XpCLKB
XpCLKFB
XpIB
XpRST#
2-16
Intel(R) 450NX PCIset
2.7 Common Support Signals
XpRSTB#
PXB Reset, 2nd Version. AGTL+ MIOC ext This is a duplicate of the XpRST# signal, to be used in maintaining PLL synchronization in the MIOC. See XpRSTFB# below. PXB Reset, Feedback. AGTL+ ext MIOC The XpRSTB# signal is length-matched to the XpRST#'s path to the PXB, then returned to the MIOC as the XpRSTFB# input.
XpRSTFB#
2.7
2.7.1
Common Support Signals
JTAG Interface
All four components in the Intel(R) 450NX PCIset have a JTAG Test Access Port (TAP) to allow access to internal registers and perform boundary scan. Each interface is identical. TCK Test Clock 2.5V I Test Clock is used to clock state information and data into and out of the device during boundary scan. Test Data Input 2.5V I Test Input is used to serially shift data and instructions into the TAP. Test Output Test Output is used to shift data out of the device. Test Mode Select Test Mode Select is used to control the state of the TAP controller. Test Reset Test Reset is used to reset the TAP controller logic. 2.5V OD
TDI
TDO
TMS
2.5V I
TRST#
2.5V I
2.7.2
Reference Signals
All four components have the following support signals to provide voltage references or compensation for the AGTL+ interfaces or the PLL circuitry. CRES[1:0] I/O Buffer Compensation Resistor Terminals Analog I For correct component operation an external 768 ohm resistor must be connected between CRES1 and CRES0. This resistor should have a minimum precision of 1%. PLL Analog Voltage Analog I This pin is an independent power supply for a PLL. In normal operation, this pin provides power to the PLL, and requires special decoupling (refer to Electrical Characteristics).
VCCA (n)
Intel(R) 450NX PCIset
2-17
2. Signal Descriptions
VREF (n)
AGTL+ Reference Voltage Analog I This is the reference voltage derived from the termination voltage to the pullup resistors. The MIOC has 6 VREF pins, while the PXB, RCG and MUX each have 2 VREF pins.
2.8
2.8.1
Component-Specific Support Signals
MIOC
CRESET# Clock Selection Reset. LVTTL O This is a delayed version of the RESET# signal provided to the processors. This signal is asserted asynchronously along with RESET#, but is deasserted two system bus clocks following the deassertion of RESET#. Error Code LVTTL I/OD These pins reflect irrecoverable errors detectable by the Intel 450NX PCIset. ERR 00 01 10 11 Error Type No error PCIset Internal Error System Bus Error Expander Bus Parity Address Parity, Request Parity, Protocol Violation, BERR, Multi-Bit Host ECC error Multi-Bit Memory Error Multi-Bit Memory ECC error Associated Error s Flags
ERR[1:0]#
HCLKIN
Host Clock In 2.5V I This pin receives a buffered system clock. This is a single trace from the clock synthesizer to minimize clock skew. Interrupt Request LVTTL O This pin is asserted by the MIOC when an internal event occurs and sets a status flag, and that flag has been configured to request an interrupt. Power Good LVTTL I This pin should be connected to a 3.3 V version of the system's power good indicator, and should be asserted only after all power supplies and clocks have reached their stable references and been stable for at least 1 msec. Buffered Power Good LVTTL O A buffered (but not synchronized) version of the PWRGD input, which is used to drive the PWRGD input on each PXB in the system. Reset AGTL+ I/O In normal operation, this signal is an output. The MIOC will reset the system bus either on power-up or when programmed through the Reset Control register.
INTREQ#
PWRGD
PWRGDB
RESET#
2-18
Intel(R) 450NX PCIset
2.8 Component-Specific Support Signals
SMIACT#
SMI Active. LVTTL O This signal provides a visible indicator that the system has entered System Management Mode.
2.8.2
PXB
INTRQ(A,B)# Interrupt Requests PCI OD These pins are asserted by the PXB when an internal event occurs and sets a status flag, and that flag has been configured to request an interrupt. There is one pin for each side (A,B) of the PXB. The signals may be connected to the standard PCI bus interrupt request lines.
PAMON[1:0]# PBMON[1:0]#
Performance Monitors LVTTL I/OD These pins track the two performance monitoring counters associated with each PCI bus (a,b) in the PXB. PMON[0] tracks the PMD[0] counter while PMON[1] tracks the PMD[1] counter. PIIX Reset Complete. LVTTL I This signal is tied to the PIIX's CPURST output, and is used to detect when the PIIX completes its reset functions. Power Good This input should be driven from the MIOC's PWRGDB output. LVTTL I
PIIXOK#
PWRGD
2.8.3
RCG
BANKID# Bank Identifier LVTTL I This strapping pin should be tied high (deasserted), or have an external pullup. 50ns DRAM "Here". LVTTL I This strapping pin selects between 60ns and 50ns DRAM timings for this RCG. Deasserted: 60ns timings will be used. Asserted: 50ns timings will be used. 50ns DRAM "There". LVTTL I This strapping pin should match the DR50H# strapping pin described above. Host Clock In This pin receives a buffered system clock. 2.5V I
DR50H#
DR50T#
HCLKIN
2.8.4
MUX
HCLKIN Host Clock In This pin receives a buffered system clock. 2.5V I
Intel(R) 450NX PCIset
2-19
2. Signal Descriptions
2-20
Intel(R) 450NX PCIset
Register Descriptions
3
The Intel(R) 450NX PCIset internal registers (both I/O Mapped and Configuration registers) are accessible by the processor. Each MIOC, and each PCI bus in each PXB has an independent configuration space. This chapter provides detailed descriptions of each register.
3.1
Access Restrictions
Register Attributes
Read Only Read/Write
Writes to this register have no effect. Data may be read from and written to this register. Selected bits in the register may be designated as "read-only"; such bits are not affected by data writes to the register. Data may be read from the register. A data write operates strictly as a clear: Data in this register remains valid and unchanged, during and following any reset except the power-good reset.
Read/Clear Sticky
3.2
I/O Mapped Registers
The Intel(R) 450NX PCIset contains two registers that reside in the processor I/O address space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.
3.2.1
CONFIG_ADDRESS: Configuration Address Register
I/O Address: Default Value: CF8h [Dword] 00000000h Size: Attribute: 32 bits Read/Write
The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.
Intel(R) 450NX PCIset
3-1
3. Register Descriptions
Bits 31
Description Configuration Enable (CFGE). When this bit is set to 1 accesses to PCI configuration space are enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled. reserved (0) Bus Number. The Bus Number field selects which PCI bus should receive the configuration cycle. The system bus and the compatibility PCI bus (PCI Bus 0A) are both accessed using Bus Number 0; which bus is accessed depends on the Device Number. Device Number. This field selects one agent on the PCI bus selected by the Bus Number. On Bus Number 0, Device Numbers 0-15 are on the compatibility PCI bus (PCI Bus 0A), while Device Numbers 16-31 refer to devices on the system bus, including the Intel 450NX PCIset itself and any Third Party Agents which use this configuration mechanism. No. Device No. Device No. Device No. Device 10h MIOC 11h reserved 14h PXB 1, Bus a 18h reserved 15h PXB 1, Bus b 19h reserved 1Ah reserved 1Bh reserved 1Ch Third Party Agent 1Dh Third Party Agent 1Eh Third Party Agent 1Fh n/a
30:24 23:16
15:11
12h PXB 0, Bus a 16h reserved 13h PXB 0, Bus b 17h reserved 10:8
Function Number. The 450NX PCIset devices are not multi-function devices, and therefore this field should always be "0" when accessing them. Register Number. This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. reserved (0)
7:2
1:0
3.2.2
CONFIG_DATA: Configuration Data Register
I/O Address: Default Value: CFCh 00000000h Size: Attribute: 32 bits Read/Write
The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Bits 31:0 Description Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1 any I/O reference that falls in the CONFIG_DATA I/O space will be mapped to configuration space using the contents of CONFIG_ADDRESS.
3-2
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
3.3
MIOC Configuration Space
Table 3-1: MIOC Configuration Space 1
DID VID 00h 04h CLASS HDR RID 08h 0Ch 10h 14h 18h 1Ch DBC 01 DBC 03 DBC 05 DBC 07 DBC 09 DBC 11 DBC 13 DBC 15 RCGP 24h 28h 2Ch 30h 34h 38h 3Ch MEL1 HEL1 MEL0 HEL0 DBC 00 DBC 02 DBC 04 DBC 06 DBC 08 DBC 10 DBC 12 DBC 14 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h
Reserved
REFRESH MEA1 MEA0
ECCMSK ECCCMD B8h BCh ROUTE0 TCAP0 TCAP1 ROUTE1 TCAP2 TCAP3 BUSNO1 SUBB0 SUBA0 SUBB1 PMD0 PMR0 PMD1 PMR1 PME1 PMD1 PMD0 C0h C4h C8h CCh BUSNO0 D0h SUBA1 D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh
CHKCON
RC ERRCMD
CONFIG ERRSTS BUFSIZ
40h 44h 48h 4Ch 50h
CVCR TOM LXGT
CVDR
LXGB HXGB HXGT
54h 58h 5Ch
DEVMAP
MAR2 MAR6 IOAR
MAR1 MAR5
MAR0 MAR4
GAPEN MAR3
60h 64h 68h 6Ch
IOABASE SMRAM MMBASE
PME0
70h 74h 78h
MMR1 MMR3 IOR
MMR0 MMR2 ISA
7Ch
1. The first 64 bytes are predefined in the PCI Specification. All other locations are defined specifically for the component of interest.
Intel(R) 450NX PCIset
3-3
3. Register Descriptions
Table 3-1 illustrates the MIOC's Configuration Space Map. Many of these registers affect both host-initiated transactions and PCI-initiated transactions, and are therefore duplicated in both the MIOC and PXB Configuration Spaces. It is software's responsibility to ensure that both sets of registers are programmed consistently to achieve correct operation.
3.3.1
BUFSIZ: Buffer Sizes
Address Offset: Default Value: Bits 23:18 48-4Ah 304310h Size: Attribute: 24 bits Read Only
Description Inbound Write Transaction Capacity. Total number of inbound write transactions, per Expander Port, that can be accepted by the MIOC. Value=12. Inbound Read Transaction Capacity. Total number of inbound read transactions, per Expander Port, that can be accepted by the MIOC. Value=4. Inbound Write Data Buffer Capacity. Total number of data buffers, per Expander Port, available in the MIOC for use by inbound write transactions, in increments of 32 bytes. Value=12. Inbound Read Data Buffer Capacity. Total number of data buffers, per Expander Port, available in the MIOC for use by inbound read transactions, in increments of 32 bytes. Value=16.
17:12
11:6
5:0
3-4
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
3.3.2
BUSNO[1:0]: Lowest PCI Bus Number, per PXB
Address Offset: Default Value: D0h, D3h 00h each Size: Attribute: 8 bits each Read/Write
The MIOC supports two Expander Ports; each can support one PXB. PXB #0 is connected to Expander Port #0, and PXB #1 is connected to Expander Port #1. Each PXB supports one or two PCI buses, connected to PCI Ports "A" and "B". The PCI bus connected to Port #0A must be the compatibility PCI bus from which a system boots. Three registers (BUSNO, SUBA and SUBB) define the bus hierarchy for each PXB. BUSNO[0] Holds the PCI-bus-number of the bus connected to PXB #0 Bus #A. This must be set to 0. Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus #A. The PCI bus number for PXB #0 Bus #B is SUBA[0]+1. Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus #B. This also represents the highest PCI-bus-number accessible from PXB #0. Holds the PCI-bus-number of the bus connected to PXB #1 Bus #A. Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus #A. The PCI bus number for PXB #1 Bus #b is SUBA[1]+1. Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus #B. This also represents the highest PCI-bus-number accessible from PXB #1 (and therefore the Intel 450NX PCIset). If PXB#1 is not in use, program this register to 0.
SUBA[0]
SUBB[0]
BUSNO[1] SUBA[1]
SUBB[1]
If PXB i is operating in 64-bit bus mode, SUBB[i] must equal SUBA[i]. Bits 7:0 Description PCI Bus Number.
NOTE Inactive PXBs should be disabled by writing the corresponding Reset Expander Port bit in the RC register and resetting the corresponding "Device present" bit in the DEVMAP register.
3.3.3
CHKCON: Check Connection
Address Offset: Default Value: Bits 7:6 43h 10h Size: Attribute: 8 bits Read/Write
Description reserved
Intel(R) 450NX PCIset
3-5
3. Register Descriptions
5
Live Port #1 Flag. If set, the port is "live". Default=0. Live Port #0 Flag. If set, the port is "live." Default=1. reserved Test Port #1 Enable. Setting this enable triggers the check connection protocol for port 1. Default=0. Test Port #0 Enable. Setting this enable triggers the check connection protocol for port 0. Default=0.
4
3:2 1
0
NOTE Setting both Test Port #1 Enable and Test Port #0 Enable simultaneously is prohibited, and will have unpredictable results, up to and including system hangs requiring a full system reset. Inactive PXBs should be disabled by writing the corresponding Reset Expander Port bit in the RC register. Transactions sent to inactive PXBs can result in system hangs.
3.3.4
CLASS: Class Code Register
Address Offset: Default Value: Bits 23:16 09 - 0Bh 060000h Size: Attribute: 24 bits Read Only
Description Base Class For the MIOC, this field is hardwired to 06h. Sub-Class For the MIOC, this field is hardwired to 00h. Register-Level Programming Interface For the MIOC this field is hardwired to 00h.
15:8
7:0
3.3.5
CONFIG: Software-Defined Configuration Register
Address Offset: Default Value: Bits 15:13 40-41h 1000h Size: Attribute: 16 bits Read/Write
Description reserved (0)
3-6
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
12
Outbound Fairness Disable. When this bit is clear, Host-PCI writes and reads that receive a retry by the MIOC follow a fairness algorithm to guarantee that retried transactions receive first priority before new transactions. If set, Host-PCI writes and reads are serviced in the order first observed without regard to retry history. Default=1. Performance Counter Master Enable (PCME). This bit provides a mechanism to (nearly) simultaneously freeze or start the performance counters across both the MIOC and PXBs. If this bit is cleared the MIOC's and PXB's performance counters will not increment If set the MIOC's and PXB's performance counters resume normal operation. Default = 0. reserved (0) Third Party Support Disable If set, performance optimizations are enabled that may result in coherency violations in the presence of a third party agent. This bit should be clear for systems with TPAs. Default = 0. External Arbiter Enable. If set, access to the system bus is controlled by an external arbiter. If cleared, the MIOC's internal arbiter is used. Default=0. WC Write Post During I/O Bridge Access Enable (UWPE). This bit should be cleared for normal operation. Default=0. Outbound I/O Write Posting Enable. If set, Host-PCI I/O writes will be posted. If cleared, Host-PCI I/O writes will not be posted. In normal operation, this enable should be set. Default=0. Read-Around-Write Enable (RAWE). If RAWE is set, it enables the read-around-write capability for the MIOC and memory subsystem. If cleared, read accesses will not advance past any previously posted writes. In normal operation, this enable should be set. Default=0. ISA Expansion Aliasing Enable. If set, every I/O access with an address in the range x100-x3FFh, x500-x7FFh, x900xBFF and xD00-xFFFh is internally aliased to the range 0100-03FFh before any other address range checking is performed. This bit only affects routing, the unmasked address is passed to the PCI bus. Default=0. reserved (0) Card to Card Interleave Enable. If set, Host or PCI accesses to memory are distributed to both memory cards on a cache line granularity. This provides a performance enhancement for systems which utilize two memory cards. When this bit is clear, C2C interleaving is disabled. Default = 0.
11
10 9
8
7
6
5
4
3 2
Intel(R) 450NX PCIset
3-7
3. Register Descriptions
1:0
Memory Address Bit Permuting. The MIOC supports cache-line permuting across banks. This field controls the type of permuting used, as follows: 00b No permuting. 01b 2-way Permuting. 10b 4-way Permuting. 11b reserved Default=0.
3.3.6
CVCR: Configuration Values Captured on Reset
Address Offset: Default Value: 4E-4Fh 0000h Size: Attribute: 16 bits Read-Only
This register captures the configuration values driven on A#[15:0] at the trailing edge of RESET#. This allows an external device to override the default values provided by the MIOC via its CVDR register. Bits 15:13 12:11 Description reserved (0) APIC Cluster ID. Captured from A#[12:11]. Represents the APIC Cluster identifier. Enable BINIT# Input. Captured from A#[10]. If set, the MIOC will observe the assertion of the BINIT# input. Further details on BINIT# processing may be found in the ERRCMD register. Enable BERR# Input. Captured from A#[9]. If set, the MIOC will observe the assertion of the BERR# input. Further details on BERR# processing may be found in the ERRCMD register. Enable AERR# Input. Captured from A#[8]. If set, the MIOC will observe the assertion of the AERR# input. Further details on AERR# processing may be found in the ERRCMD register. If this enable is asserted, then the BINIT# Driver Enable in the ERRCMD register must also be asserted. In-Order Queue Depth 1. Captured from A#[7]. If set, the MIOC will limit its In-Order Queue Depth to 1 (no pipelining support), instead of the usual 8. 1M Power-on Reset Vector. Captured from A#[6]. This bit has no meaning for the MIOC. If set, all Pentium(R) II XeonTM processors on the system bus will use the 1MB-1 (000FFFFFh) reset vector, instead of their usual 4 GB-1 (FFFFFFFFh) vector. Enable FRC Mode. Captured from A#[5]. This bit has no meaning for the MIOC. If set, all Pentium II Xeon processors on the system bus will enter FRC-enabled mode. reserved (0)
Intel(R) 450NX PCIset
10
9
8
7
6
5
4:0 3-8
3.3 MIOC Configuration Space
3.3.7
CVDR: Configuration Values Driven On Reset
Address Offset: Default Value: 4C-4Dh 0000h Size: Attribute: 16 bits Read/Write, Sticky
During RESET# assertion, and for one host clock past the trailing edge of RESET#, the MIOC drives the contents of this register onto the A[15:0]# pins. Bits 15:13 12:11 Description reserved (0) APIC Cluster ID. This two-bit field representing the APIC Cluster identifier is driven to A#[12:11] during RESET#. Note that there are no pins to input the cluster ID; software must explicitly load the value into this register. Default=0. reserved (0) Enable BERR# Input. If set, A#[9] will be asserted during RESET#, and all system bus agents will enable BERR# observation. Default=0. Enable AERR# Input. If set, A#[8] will be asserted during RESET#, and all system bus agents will enable AERR# observation. Default=0. In-Order Queue Depth 1. If set, A#[7] will be asserted during RESET#, and all Pentium(R) II XeonTM processors on the system bus will limit their In-Order Queue Depth to 1 (no pipelining support), instead of their usual 8. Default=0. 1M Power-on Reset Vector. If set, A#[6] will be asserted during RESET#, and all Pentium II Xeon processors on the system bus will use the 1MB-1 (000FFFFFh) reset vector, instead of their usual 4 GB-1 (FFFFFFFFh) vector. Default=0. Enable FRC Mode. If set, A#[5] will be asserted during RESET#, and all Pentium II Xeon processors on the system bus will enter FRC enabled mode. Default=0. reserved (0)
10 9
8
7
6
5
4:0
3.3.8
DBC[15:0]: DRAM Bank Configuration Registers
Address Offset: Default Value: 80-9Fh A200h each Size: Attribute: 16 bits each Read/Write
The Intel 450NX PCIset memory subsystem supports at most two RCGs (one RCG and four banks per card) for a maximum of 8 GB of memory. This corresponds to DBC[0:3] on the first card and DBC[8:11] on the second card.
Intel(R) 450NX PCIset
3-9
3. Register Descriptions
Unused DBC registers should be configured as inactive, with the Bank Present bit cleared and the TOB field set to that of the previous bank, indicating that the amount of memory in that bank is zero. Bits 15 Description 4:1 Interleave. If set, bank is a 4:1 interleave. If cleared, bank is a 2:1 interleave. Default=1. Single Row. This bit is set if the bank contains only a single row. If cleared, the bank contains two rows; both rows must be configured identically. Default=0. Bank Present. This bit is set to indicate that this memory bank is present, and refresh cycles should be issued to the bank. This bit must be cleared if this bank is not physically present. Default=1. reserved (0) Top of Bank (TOB). This field contains the effective address of the top of memory in this bank and all lower banks, and is used to determine which bank is selected. Each TOB field specifies the amount of memory, in 32 MB chunks, contained in this bank and all lower banks. Unpopulated banks must have their TOB set equal to that of the previous bank indicating that the amount of memory in that bank is zero. Default = 200h, each.
14
13
12:10 9:0
3.3.9
DEVMAP: System Bus PCI Device Map
Address Offset: Default Value: D6-D7h 0005h Size: Attribute: 16 bits Read/Write, Read Only
This register indicates which PCI devices on the system bus have active configuration spaces. At reset, DEVMAP is initialized with all devices not present except the MIOC and the compatibility PCI bus. Bits 15 14:0 Description reserved (0) PCI Bus #0, Device [30:16] Present. Each bit corresponds to a device on PCI Bus #0 (numbers 16-30). If set, the device is present in the system and is expected to respond to configuration cycles directed to it. Bit 0 is hardwired "on", and is read-only. Default=0005h (MIOC, PCI #0A present)
3-10
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
3.3.10
DID: Device Identification Register
Address Offset: Default Value: Bits 15:0 02 - 03h 84CAh Size: 16 bits Attributes: Read Only
Description Device Identification Number. The value 84CAh indicates the Intel(R) 450NX PCIset MIOC.
3.3.11
ECCCMD: ECC Command Register
Address Offset: Default Value: B8h 00h Size: Attribute: 8 bits Read/Write
This register controls the Intel 450NX PCIset responses to ECC errors on data retrieved from the memory subsystem or received from the system bus. Bits 7 6 Description reserved (0) System Bus, Report Multi-Bit Errors (HRM). If set, the Intel(R) 450NX PCIset will log multiple-bit ECC errors on data received from the system bus in the appropriate HEL register. If the BERR# driver is enabled, BERR# will also be asserted. Default=0. System Bus, Report Single-Bit Errors (HRS). If set, on detection of a single-bit ECC error on data received from the system bus the Intel 450NX PCIset will log the error in the appropriate HEL register, and assert the INTREQ# signal. Default=0. System Bus, Correct Single-Bit Errors (HCS). If set, on detection of a single-bit ECC error on data received from the system bus the Intel 450NX PCIset will correct the data and generate a new ECC code before writing the data into memory. Default=0. Memory, Scrub Single-Bit Errors (MSS). If set, on detection of a single-bit ECC error on data read from the memory array the Intel 450NX PCIset will perform a scrub operation to correct the location in the memory. The MCS bit in this register must be set for this feature to be effective. Default=0. Memory, Report Multi-Bit Errors (MRM). If set, on detection of a multiple-bit ECC error on data read from the memory array the Intel 450NX PCIset will log the error in the appropriate MEL and MEA registers. If the BERR# driver is enabled, BERR# will also be asserted. Default=0.
5
4
3
2
Intel(R) 450NX PCIset
3-11
3. Register Descriptions
1
Memory, Report Single-Bit Errors (MRS). If set, on detection of a single-bit ECC error on data read from the memory array the Intel 450NX PCIset will log the error in the appropriate MEL and MEA registers, and assert the INTREQ# signal. Default=0. Memory, Correct Single-Bit Errors (MCS). If set, on detection of a single-bit ECC error on data read from the memory array the Intel 450NX PCIset will correct the data and generate a new ECC code before returning the data to the requestor. Default=0.
0
3.3.12
ECCMSK: ECC Mask Register
Address Offset: Default Value: B9h 00h Size: Attribute: 8 bits Read/Write
This register is used to test the ECC error detection logic in the memory subsystem. The register is written with a masking function which is applied on subsequent writes to memory. All subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of the memory locations written while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (default). Bits 7:0 Description ECC Generation Mask. Each bit of the computed ECC is XOR'ed with the corresponding bit in this mask field before it is stored in the memory array.
3.3.13
ERRCMD: Error Command Register
Address Offset: Default Value: 46h 00h Size: Attribute: 8 bits Read/Write
This register controls the MIOC responses to various system and data errors. Bits 7:6 5 Description reserved (0) BERR#-to-BINIT# Enable. If set, on observation or assertion of BERR#, (and Enable BERR# Input is set) the MIOC will also assert BINIT#. Default=0. Fast System Bus Time-out. This bit controls the duration of a watchdog timer which is started at the end of the system bus response phase. If this bit is set, the timer expires in 256 host cycles. If cleared, the timer expires in 217 cycles. Default=0.
4
3-12
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
3
BINIT# on System Bus Time-outs. If this bit is set, and the BINIT# Driver Enable is set, the MIOC will assert BINIT# on a system bus access time-out. Default=0. AERR# Driver Enable. If set, parity errors on the system bus address and request signals are reported by asserting AERR#. Default=0. BERR# Driver Enable. If set, BERR# will be asserted for uncorrectable ECC errors on memory reads or data arriving from the system data bus. Default=0. BINIT# Driver Enable. If set, BINIT# will be asserted upon detecting protocol violations on the system bus. This enable should only be cleared for system boot. In normal operation, this enable must be set. Default=0.
2
1
0
3.3.14
ERRSTS: Error Status Register
Address Offset: Default Value: 44-45h 0000h Size: Attribute: 16 bits Read/Write Clear, Sticky
This register records error conditions detected in the address or controls of the system bus, or in the MIOC itself. Recording of these error conditions is controlled via the ERRCMD register. ERRSTS is sticky through reset, and bits will remain set until explicitly cleared by software writing a 1 to the bit. Bits 15:13 12 Description reserved (0) Received Hard Fail Response on System Bus. This flag is set when the MIOC detects a Hard Fail response on the system bus. If the BINIT# Driver Enable in the ERRCMD register is set, BINIT# is also asserted. Expander Bus #1 Protocol Violation Flag. This flag is set when the Expander Bus #1 interface receives unexpected data that the MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is also asserted. Expander Bus #0 Protocol Violation Flag. This flag is set when the Expander Bus #0 interface receives unexpected data that the MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is also asserted. Performance Monitor #1 Event Flag. This flag is set when the Performance Monitor #1 requests that an interrupt request be asserted. While this bit is set, the INTREQ# line will be asserted. Performance Monitor #0 Event Flag. This flag is set when the Performance Monitor #0 requests that an interrupt request be asserted. While this bit is set, the INTREQ# line will be asserted.
11
10
9
8
Intel(R) 450NX PCIset
3-13
3. Register Descriptions
7 6
reserved (0) System Bus Time-out Flag. This flag is set when the watchdog timer monitoring accesses on the system bus times out. See the BINIT#-on-System-Bus-Time-outs Enable and the BINIT# Driver Enable in the ERRCMD register. Expander Bus 1 Parity Error Flag. This flag is set when Expander Bus #1 reports a parity error on data inbound from the PXB. This condition is a catastrophic fail and will also assert BINIT#. Expander Bus 0 Parity Error Flag. This flag is set when Expander Bus #0 reports a parity error on data inbound from the PXB. This condition is a catastrophic fail and will also assert BINIT#. BERR# Error Flag. This flag is set when BERR# is detected asserted on the system bus. Address Parity Error. This flag is set upon detecting the assertion of AP#, indicating a parity error on the system address signals. If the AERR# Driver Enable is set in the ERRCMD register, AERR# is asserted. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is asserted. Response Parity Error Flag. This flag is set upon detecting the assertion of RP#, indicating a parity error on the system bus response signals. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is also asserted. Request Parity Error. This flag is set upon detecting the assertion of RP#, indicating an error on ADS or request signals. If the AERR# Driver Enable is set in the ERRCMD register, AERR# is asserted. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is asserted.
5
4
3
2
1
0
3.3.15
GAPEN: Gap Enables
Address Offset: Default Value: Bits 7 6 60h 0Eh Size: Attribute: 8 bits Read/Write
Description reserved (0) ISA Space Enable. When set, the ISA Space address range is enabled. Memory-mapped accesses that fall within this address range are forwarded to the compatibility PCI bus. If this bit is cleared, accesses to this address range are handled normally. Default=0. High Expansion Gap Enable. When set, the High Expansion Gap (HXG) is enabled. Default=0.
5
3-14
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
4
Low Expansion Gap Enable. When set, the Low Expansion Gap (LXG) is enabled. Default=0. High BIOS Space Enable. If set, a 2 MByte space is opened at location (4 GB - 2 MB), and accesses into this address range will be directed to the compatibility PCI bus instead of memory. Default=1. High Graphics Adapter Space Enable. If set, a 64 KB space is opened in the upper half of the Graphics Adapter portion of the Low Compatibility Region (address range B_0000h-BFFFFh), and accesses into this address range will be directed to the compatibility PCI bus instead of memory. Default=1. Low Graphics Adapter Space Enable. If set, a 64 KB space is opened in the lower half of the Graphics Adapter portion of the Low Compatibility Region (address range A_0000h-AFFFFh), and accesses into this address will be directed to the compatibility PCI bus instead of memory. Default=1. reserved (0)
3
2
1
0
3.3.16
HDR: Header Type Register
Address Offset: Default Value: 0Eh 00h Size: Attribute: 8 bits Read Only
This register identifies the header layout of the configuration space. Writes to this register have no effect. Bits 7 Description Multi-function Device. The MIOC is not a multi-function device, and this bit is hardwired to 0. Configuration Layout. This field is hardwired to 00h, which represents the default PCI configuration layout.
6:0
3.3.17
HEL[1:0] Host Bus Error Log
Address Offset: Default Value: B4-B7h 0000h each Size: Attribute: 16 bits each Read/Write, Sticky
These registers are loaded on the first and second ECC errors detected on data received from the system bus. HEL[0] logs the first error, and HEL[1] logs the second. The registers hold their data until reloaded due to a new error condition, or until they are explicitly cleared by software or a power-good reset.
Intel(R) 450NX PCIset
3-15
3. Register Descriptions
Bits 15:8
Description Syndrome. Holds the calculated syndrome that identifies the specific bit in error. reserved (0) Multiple-Bit Error Logged (MBE). This flag is set if the logged error was a multiple-bit (uncorrectable) error. Single-Bit Error Logged (SBE). This flag is set if the logged error was a single-bit (correctable) error.
7:2 1
0
3.3.18
HXGB: High Expansion Gap Base
Address Offset: Default Value: Bits 23:0 58-5Ah 000000h Size: Attribute: 24 bits Read/Write
Description Gap Base Address. This field specifies the A[43:20] portion of the gap's base address, in 1 MB increments. The A[19:0] portions of the gap's base address are zero.
3.3.19
HXGT: High Expansion Gap Top
Address Offset: Default Value: Bits 23:0 5C-5Eh 000000h Size: Attribute: 24 bits Read/Write
Description Gap Top Address. This field specifies the A[43:20] portion of the gap's highest address, in 1 MB increments. The A[19:0] portion of the gap's top address is FFFFFh.
3.3.20
IOABASE: I/O APIC Base Address
Address Offset: Default Value: Bits 15:12 11:0 68-69h 0FECh Size: Attribute: 16 bits Read/Write
Description reserved (0) I/O APIC Base Address. This field specifies the A[31:20] portion of the I/O APIC Space's base address, in 1 MB increments. The A[43:32] and A[19:0] portions of the address are zero.
3-16
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
3.3.21
IOAR: I/O APIC Ranges
Address Offset: Default Value: 6A-6Bh 0000h Size: Attribute: 16 bits Read/Write
Each of the three fields in the IOAR register specifies the highest APIC number (0-15) that should be directed to that PCI bus, for buses 0A, 0B and 1A. All higher APIC ID are directed to PCI Bus 1B. Bits 15:12 11:8 Description reserved (0) PCI Bus #1A Highest APIC ID (BUS1A). This field represents the highest APIC ID that should be directed to PCI Bus #1A. PCI Bus #0B Highest APIC ID (BUS0B). This field represents the highest APIC ID that should be directed to PCI Bus #0B. PCI Bus #0A Highest APIC ID (BUS0A). This field represents the highest APIC ID that should be directed to PCI Bus #0A.
7:4
3:0
3.3.22
IOR: I/O Ranges
Address Offset: Default Value: 7E-7Fh 0FFFh Size: Attribute: 16 bits Read/Write
The IOR register defines the I/O range addresses for each PCI bus. These are specified in sixteen 4 KB segments. The starting (base) address for PCI Bus #0A is 0h. Bits 15:12 11:8 Description reserved (0) PCI Bus #1A Upper Address (BUS1A). This field represents the A[15:12] portion of the highest I/O address that should be directed to PCI Bus #1A. The A[11:0] portion of this address is FFFh. PCI Bus #0B Upper Address (BUS0B). This field represents the A[15:12] portion of the highest I/O address that should be directed to PCI Bus #0B. The A[11:0] portion of this address is FFFh. PCI Bus #0A Upper Address (BUS0A). This field represents the A[15:12] portion of the highest I/O address that should be directed to PCI Bus #0A. The A[11:0] portion of this address is FFFh.
7:4
3:0
If PXB x is operating in 64-bit bus mode, BUSxB must equal BUSxA.
Intel(R) 450NX PCIset
3-17
3. Register Descriptions
3.3.23
ISA: ISA Space
Address Offset: Default Value: 7Ch 00h Size: Attribute: 8 bits Read/Write
This register defines the ISA Space address range. If enabled, memory-mapped accesses into this address range will be forwarded to the compatibility PCI bus. This space is defined to support ISA cards incapable of using the full 32-bit PCI address. Bits 7:6 5:4 Description reserved (0) ISA Space Size. This field specifies the size of the gap. Legal sizes are: 00b: 1 MB 10b: 4 MB 01b: 2 MB 11b: 8 MB ISA Space Base Address. This 4-bit field specifies the A[23:20] portion of the gap's base address. The A[43:24] and A[19:0] portions of the gap's base address are zero.
3:0
3.3.24
LXGB: Low Expansion Gap Base
Address Offset: Default Value: Bits 15:12 11:0 54-55h 0000h Size: Attribute: 16 bits Read/Write
Description reserved (0) Gap Base Address. This field specifies the A[31:20] portion of the gap's base address, in 1 MB increments. The A[43:32] and A[19:0] portions of the gap's base address are zero.
3.3.25
LXGT: Low Expansion Gap Top
Address Offset: Default Value: Bits 15:12 11:0 56-57h 0000h Size: Attribute: 16 bits Read/Write
Description reserved (0) Gap Top Address. This field specifies the A[31:20] portion of the gap's highest address, in 1 MB increments. The A[43:32] portion of the gap's top address is zero, while the A[19:0] portion of the gap's top address is FFFFFh.
3-18
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
3.3.26
MAR[6:0]: Memory Attribute Region Registers
Address Offset: Default Value: 61-67h 03h for MAR[0] 00h for all others Size: Attribute: 8 bits each Read/Write
Seven Memory Attribute Region (MAR) registers are used to program memory attributes of various sizes in the 640 Kbyte-1 MByte address range. Each MAR register controls two segments, typically 16 Kbyte in size. Each of these segments has an identical 4-bit field which specifies the memory attributes for the segment, and apply to both host-initiated accesses and PCI-initiated accesses to the segment. Bits 7:6 5 Description reserved (0) Segment 1, Write Enable (WE). When cleared, host-initiated write accesses are directed to the compatibility PCI bus. When set, write accesses are handled normally according to the outbound access disposition. Segment 1, Read Enable (RE). When cleared, host-initiated read accesses are directed to the compatibility PCI bus. When set, read accesses are handled normally according to the outbound access disposition. reserved (0) Segment 0, Write Enable (WE). Identical to segment 1 WE, above. Segment 0, Read Enable (RE). Identical to segment 1 RE, above.
4
3:2 1
0
Table 3-2 summarizes the possible outcomes of the various Read Enable (RE) and Write Enable (WE) combinations: Table 3-2: MAR-controlled Access Disposition WE, RE 00 01 10 11 Outbound Write PCI 0a PCI 0a Memory1 Memory
1
Outbound locked Write PCI 0a PCI 0a PCI 0a
1
Inbound Write unclaimed unclaimed Memory 2
1
Read PCI 0a Memory1 PCI 0a Memory
Read PCI 0a PCI 0a PCI 0a
Read unclaimed Memory2 unclaimed Memory2
Memory
1
Memory
Memory
2
1. Normally, the access will be directed to the DRAM. However, if this MAR region is overlapped by an enabled expansion gap, the access will instead be left unclaimed on the system bus. A thirdparty agent may then claim the access. 2. Normally, the access will be directed to the DRAM. However, if this MAR region is overlapped by an enabled expansion gap, the access will instead be directed up to the system bus. A third-party agent may then claim the access.
Intel(R) 450NX PCIset
3-19
3. Register Descriptions
3.3.27
MEA[1:0] Memory Error Effective Address
Address Offset: Default Value: A8-A9h 00h each Size: Attribute: 8 bits each Read/Write, Sticky
These registers contain the effective address information needed to identify the specific DIMM that produced the error. Bits 7 Description Card. Holds the card number (0,1) where the suspect DIMM resides. Bank. Identifies the bank within the card (0..7) where the suspect DIMM resides. Row. Identifies the row within the bank (for double row DIMMs). reserved (0) Effective Address [4:3]. These two bits of the effective address indicate the "starting" Qword in the critical order access. When combined with the chunk number of the error, as logged in the MEL registers, this identifies the specific DIMM where the error occurred.
6:4
3
2 1:0
3.3.28
MEL[1:0] Memory Error Log
Address Offset: Default Value: B0-B3h 0000h each Size: Attribute: 16 bits each Read/Write, Sticky
These registers are loaded on the first and second ECC errors detected on data retrieved from the memory. MEL[0] logs the first error, and MEL[1] logs the second. Bits 15:8 Description Syndrome. Holds the calculated syndrome that identifies the specific bit in error. reserved (0) Chunk Number. Specifies which of the four possible chunks in the critical chunk ordered transfer the error occurred in, from zero to three. Multiple-Bit Error Logged (MBE). This flag is set if the logged error was a multiple-bit (uncorrectable) error. Single-Bit Error Logged (SBE). This flag is set if the logged error was a single-bit (correctable) error.
7:4 3:2
1
0
3-20
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
3.3.29
MMBASE: Memory-Mapped PCI Base
Address Offset: Default Value: 70-71h 0002h Size: Attribute: 16 bits Read/Write
The MMBASE register defines the starting address of the Memory-Mapped PCI Space, and each MMR register defines the highest address to be directed to a PCI bus. If PXB 0 is operating in 64-bit bus mode, MMR[0] must equal MMBASE. If PXB 1 is operating in 64-bit bus mode, MMR[3] must equal MMR[2]. Bits 15:12 11:0 Description reserved (0) PCI Space Base Address. This field specifies the A[31:20] portion of the PCI space's base address, in 1MB increments. The A[43:32] and A[19:0] portions of the address are zero.
3.3.30
MMR[3:0]: Memory-Mapped PCI Ranges
Address Offset: Default Value: 74-7Bh 0001h each Size: Attribute: 16 bits each Read/Write
These registers define the high addresses for addresses to be directed to the PCI space. Bits 15:12 11:0 Description reserved (0) PCI Space Top Address. This field specifies the A[31:20] portion of the PCI space's highest address, in 1 MB increments. The A[43:32] portion of this address is zero, while the A[19:0] portion of this address is FFFFFh.
3.3.31
PMD[1:0]: Performance Monitoring Data Register
Address Offset: Default Value: D8-DCh, E0-E4h 0000000000h each Size: Attribute: 40 bits each Read/Write
Two performance monitoring counters are provided in the MIOC. The PMD registers hold the performance monitoring count values. Each counter can be configured to reload the data when it, or the other counter overflows. Event selection is controlled by the PME registers, and the action performed on event detection is controlled by the PMR registers. An additional Performance Counter Master Enable (PCME) in the MIOC's CONFIG register allows (nearly) simultaneous stopping/starting of all counters in the MIOC and each PXB. The counters cannot be read or written coherently while the counters are running.
Intel(R) 450NX PCIset
3-21
3. Register Descriptions
Bits 39:0
Description Count Value.
3.3.32
PME[1:0]: Performance Monitoring Event Selection
Address Offset: Default Value: Bits 15 14 E8-E9h, EA-EBh 0000h each Size: Attribute: 16 bits each Read/Write
Description reserved (0) Count Data Cycles 1: Count the request length of the selected transaction. 0: Count the selected event reserved (0) Initiating Agent Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions issued by specific agents. 000 Symmetric Agent 0 (DID=0/000) 100 Any symmetric agent (DID=0/xxx) 001 Symmetric Agent 1 (DID=0/001) 101 Third party agent (DID=1/other) 010 Symmetric Agent 2 (DID=0/010) 110 Intel(R) 450NX PCIset agent (DID=1/001) 011 Symmetric Agent 3 (DID=0/011) 111 Any agent Transaction Destination Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions directed to a specific resource. 00 Any 10 Not Third Party or Memory1 01 Main Memory 11 Third party
1. The usual destination in this category is a PCI Target. Also included are Internal CFC/CF8 accesses, Branch trace messages, Interrupt acknowledge, and some special transactions.
13 12:10
9:8
7:6
Data Length Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions of a specific length. 00 Any 10 Part-lines or partials 01 Lines 11 reserved Event Selection. This field specifies the basic system bus transaction, system bus signal assertion, or memory event to be monitored. Individual Bus Transactions 00 0000 Deferred Reply 00 1000 reserved 00 0001 reserved 00 1001 reserved 00 0010 reserved 00 1010 Memory Read Invalidate 00 0011 reserved 00 1011 reserved 00 0100 I/O Read 00 1100 Memory Read Code 00 0101 I/O Write 00 1101 Memory Writeback
5:0
3-22
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
00 0110 reserved 00 0111 reserved Generic (Grouped) Bus Transactions 010 000 Any bus transaction 010 001 Any memory transaction 010 010 Any memory read 010 011 Any memory write Bus Signal Assertions 011 000 HIT1,2 011 001 HITM1,2 011 010 RETRY1,2 011 011 DEFER1,2 Memory Hits/Misses 100 000 Bank was idle1,2 100 001 Waited for Row precharge1,2 All other encodings are reserved.
00 1110 00 1111 010 100 010 101 010 110 010 111 011 100 011 101 011 110 011 111 100 010 100 011
Memory Read Memory Write Any I/O transaction Any I/O or memory transactions Any I/O or memory read Any I/O or memory write BNR1,2 BPRI2 LOCK2 reserved Waited for address lines1,2 Hit open page1,2
Notes: 1. Counting data cycles is undefined for this selection. 2. The Agent, Destination and Length fields cannot be applied to this selection, and should be programmed to "any".
3.3.33
PMR[1:0]: Performance Monitoring Response
Address Offset: Default Value: DDh, E5h 00h each Size: Attribute: 8 bits each Read/Write
The PMR register specifies how the event selected by the corresponding PME register affects the associated PMD register, the BP[1:0] pins, and the INTREQ# pin. Events defined by PME[0] can be driven out BP0 and events defined by PME[1] can be driven out BP1. Bits 7:6 Description Interrupt Assertion Defines how selected event affects INTREQ# assertion. Whenever INTREQ# is asserted, a flag for this counter is set in the Error Status (ERRSTS) register, so that software can determine the cause of the interrupt. This flag is reset by writing the ERRSTS register. 0 Selected event does not assert INTREQ# reserved 1 2 Assert INTREQ# pin when event occurs 3 Assert INTREQ# pin when counter overflows Performance Monitoring pin assertion Defines how the selected event affects the Performance Monitoring pin for this counter. 0 Selected event does not assert this counters PM pin reserved 1 2 Assert this counter's PM pin when event occurs 3 Assert this counter's PM pin when counter overflows
5:4
Intel(R) 450NX PCIset
3-23
3. Register Descriptions
3:2
Count Mode Selects when the counter is updated for the detected event. 0 Stop counting. 1 Count each cycle selected event occurs. 2 Count on each rising edge of the selected event. 3 Trigger. Start counting on the first rising edge of the selected event, and continue counting each clock cycle. Reload Mode Reload has priority over increment. If a reload event and a count event happen simultaneously, the count event has no effect. 0 Never Reload 1 Reload when this counter overflows. 2 Reload when the other counter overflows. 3 Reload unless the other counter increments.
1:0
3.3.34
RC: Reset Control Register
Address Offset: Default Value: 42h 00h Size: Attribute: 8 bits Read/Write
The RC initiates processor reset cycles and initiates Built-in Self Test (BIST) for the processors. Bits 7:6 5 Description reserved (0) Reset Expander Port #1. While this bit is set, the X1RST# signal is asserted. When this bit is cleared, the X1RST# pin will be deasserted, unless other assertion criteria are still in effect (e.g., system hard reset). Default=0. Reset Expander Port #0. While this bit is set, the X0RST# signal is asserted. When this bit is cleared, the X0RST# will be deasserted, unless other assertion criteria are still in effect (e.g., system hard reset). Default=0. Processor BIST Enable (BISTE). This bit modifies the action of the RCPU and SHRE bits, below. If this bit is set, a subsequent invocation of system hard reset causes the INIT# signal to be asserted coincident with the deassertion of RESET#; this combination will invoke the Built-In Self Test (BIST) feature of the processors. Default=0. Reset Processor (RCPU). The transition of this bit from 0 to 1 causes the MIOC to initiate a hard or soft reset. Selection of hard or soft reset, and processor BIST, are controlled by the BISTE and SHRE enables, which must be set up prior to the 0-to-1 transition on the RCPU bit. Default=0.
4
3
2
3-24
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
1
System Hard Reset Enable (SHRE). This bit modifies the action of the RCPU bit, above. If set, the Intel(R) 450NX PCIset will initiate a system hard reset upon a subsequent 0-to-1 transition of the RCPU bit. If this bit is cleared, the Intel 450NX PCIset will initiate a soft reset upon a subsequent 0to-1 transition of the RCPU bit. Default=0. reserved (0)
0
3.3.35
RCGP: RCGs Present
Address Offset: Default Value: A3h 00h Size: Attribute: 8 bits Read/Write
The Intel 450NX PCIset memory subsystem supports at most two RCGs (one per card). This corresponds to RCG #0 and RCG #2, bits 0 and 2 in the RCGP register. Bits 7:4 3:0 Description reserved (0) RCGs Present [3:0]. If bit i is set, then RCG[i] was detected as present in the system following power-on reset. If cleared, then RCG[i] is not present. Default= .
3.3.36
REFRESH: DRAM Refresh Control Register
Address Offset: Default Value: Bits 15:11 10:0 A4-A5h 0411h Size: Attribute: 16 bits Read/Write
Description reserved (0) Refresh Count. Specifies the number of system bus cycles between refresh cycles. Typically, the value is chosen to provide a refresh at least every 15.625 usec. @ 100.0 MHz: 61Ah = 15.620 usec @ 90.0 MHz: 57Eh = 15.622 usec Maximum value is 20.48 usec at 100 MHz. Default=411h
3.3.37
RID: Revision Identification Register
Address Offset: Default Value: 08h 00h Size: Attribute: 8 bits Read Only
Intel(R) 450NX PCIset
3-25
3. Register Descriptions
Bits 7:0
Description Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the MIOC
3.3.38
ROUTE[1:0]: Route Field Seed
Address Offset: Default Value: Bits 7:4 C3h, CBh 40h Size: Attribute: 8 bits Read/Write
Description Outbound-to-B Route Seed. This field represents the "seed" value used to create the routing field for outbound packets to the PXB's B-port. Default: 0100b Outbound-to-A Route Seed. This field represents the "seed" value used to create the routing field for outbound packets to the PXB's A-port. Default: 0000b
3:0
3.3.39
SMRAM: SMM RAM Control Register
Address Offset: Default Value: Bits 31 6C-6Fh 00000Ah Size: Attribute: 32 bits Read/Write
Description SMRAM Enable (SMRAME). If set, the SMRAM functions are enabled. Host-initiated accesses to the SMM space can be selectively directed to memory or PCI, as defined below and in Table 3-3. If SMRAME is cleared, SMRAM functions are disabled. Default=0. reserved (0) SMM Space Open (D_OPEN). If set, all accesses (code fetches or data references) to SMM space are passed to memory, regardless of whether the SMMEM# signal is asserted. D_OPEN may be set or cleared by software. D_OPEN will also be automatically cleared, and will become read-only, when the D_LCK enable is set. Default=0. SMM Space Closed (D_CODE). This bit should not be set unless D_OPEN=0. If D_CODE is set, only code fetches to SMM space may be passed to the DRAM, depending on the SMMEM# signal. Data accesses to SMM space will not be passed to the DRAM, regardless of the SMMEM# signal. Default=0.
30:27 26
25
3-26
Intel(R) 450NX PCIset
3.3 MIOC Configuration Space
24
SMM Space Locked (D_LCK). When software writes a 1 to this bit, the hardware will clear the D_OPEN bit, and both D_LCK and D_OPEN then become read only. No application software, except the SMI handler, should violate or change the contents of SMM memory. Default=0. SMM Space Size. This field specifies the size of the SMM RAM space, in 64 KB increments. 0h 4h 320 KB 8h 576 KB Ch 832 KB 64 KB 1h 128 KB 5h 384 KB 9h 640 KB Dh 896 KB 2h 192 KB 6h 448 KB Ah 704 KB Eh 960 KB 3h 256 KB 7h 512 KB Bh 768 KB Fh 1 MB Default: 0h (64 KB).
23:20
19:16 15:0
reserved (0) SMM Space Base Address. This field specifies the A[31:16] portion of the SMM RAM space base address (A[15:0]=0000h). The space may be relocated anywhere below the 4 GB boundary and the Top of Memory (TOM); however, the base address must be aligned on the next highest power-of-2 natural boundary given the chosen size. Incorrect alignment results in indeterminate operation. Default: 000Ah. Table 3-3: SMRAM Space Cycles
SMRAME
D_CODE
D_OPEN
SMMEM
D_LCK
Code Fetch Normal1 PCI 0a DRAM
Data Reference Normal1 PCI 0A DRAM
Usage
0 1 1
X 0 0
X 0 0
X X X
X 0 1
SMM RAM space is not supported. Normal SMM usage. Accesses to the SMM RAM space from processors in SMM will access the DRAM. Accesses by processors not in SMM will be diverted to the compatibility PCI bus. A modification of the normal SMM usage, in which only code fetches are accepted from processors in SMM mode. Full access by any agent to SMM RAM space.
1 1 X 1
0 0 1 1
1 1 1 0
X X X 0
0 1 X X
PCI 0A DRAM
PCI 0A PCI 0A
Illegal Combination DRAM DRAM
1. SMRAM functions are disabled.
3.3.40
SUBA[1:0]: Bus A Subordinate Bus Number, per PXB
Address Offset: Default Value: D1h, D4h 00h each Size: Attribute: 8 bits each Read/Write
See the description of BUSNO.
Intel(R) 450NX PCIset
3-27
3. Register Descriptions
3.3.41
SUBB[1:0]: Bus B Subordinate Bus Number, per PXB
Address Offset: Default Value: D2h, D5h 00h each Size: Attribute: 8 bits each Read/Write
See the description of BUSNO.
3.3.42
TCAP[0:3]: Target Capacity, per PXB/PCI Port
Address Offset: Default Value: C0-C2h, C4-C6h C8-CAh, CC-CEh 041082 each Size: Attribute: 24 bits each Read/Write
Each of these registers is programmed by software with the maximum number of transactions and data bytes that the receiving PXB/PCI port can accept for outbound transactions. Register TCAP[0] TCAP[1] TCAP[2] TCAP[3] Controls outbound transactions to ... if in ... dual 32-bit Bus Mode PXB #0 / PCI Bus A PXB #0 / PCI Bus B PXB #1 / PCI Bus A PXB #1/ PCI Bus B 64-bit Bus Mode PXB #0 N/A PXB #0 N/A
NOTE Setting a value below the listed minimum-allowed value will have unpredictable results, up to and including potential deadlocks requiring a hard reset of the PCIset.
Bits 23:18
Description Outbound Write Transaction Capacity. This field specifies the total number of outbound write transactions, per PXB/PCI port, that can be forwarded and queued by the PXB. MIOC maximum: 12 Minimum allowed: 1, 2 or 3 Default= 1
- If no outbound locks are supported, then the minimum is 1. - If ordinary outbound locks are supported, then the minimum is 2. - If outbound split locks are supported, then the minimum is 3. 17:12 Outbound Read Transaction Capacity. This field specifies the total number of outbound read transactions, per PXB/PCI port, that can be forwarded and queued in the PXB. Minimum allowed: 1 Default= 1
MIOC maximum: 2 11:6
Outbound Write Data Buffer Capacity. This field specifies the total number of data buffers, per PXB/PCI port, available in the PXB for use by outbound write transactions, in increments of 32 bytes. MIOC maximum: 12 Minimum allowed: 2 Default= 2
3-28
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
5:0
Outbound Read Data Buffer Capacity. This field specifies the total number of data buffers, per PXB/PCI port, available in the PXB for use by outbound read transactions, in increments of 32 bytes. MIOC maximum: 16 Minimum allowed: 2 Default= 2
3.3.43
TOM: Top of Memory
Address Offset: Default Value: Bits 23:0 50-52h 000FFFh Size: Attribute: 24 bits Read/Write
Description Memory Address Ceiling. Represents bits A[43:20] of the highest physical address to be directed toward this node's DRAM. The lower A[19:0] bits of this address are FFFFFh. Default=000FFFh (4 GB-1).
3.3.44
VID: Vendor Identification Register
Address Offset: Default Value: Bits 15:0 00 - 01h 8086h Size: 16 bits Attributes: Read Only
Description Vendor Identification Number. This is a 16-bit value assigned to Intel.
Intel VID = 8086h.
3.4
PXB Configuration Space
Each PXB supports two independent PCI buses (Bus "A" and Bus "B"), which can be configured independently. Each PCI bus therefore has its own configuration space. Both configuration spaces are identical. When operating the PXB in 64-bit Bus Mode, only the Aside configuration space is used. The B-side configuration space is not accessible while in 64bit mode. Table 3-4 illustrates the PXB/PCI Bus Configuration Space Map.
Intel(R) 450NX PCIset
3-29
3. Register Descriptions
Table 3-4: PXB Configuration Space 1
DID PCISTS CLASS HDR MLT VID PCICMD RID CLS 00h 04h 08h 0Ch 10h 14h 18h 1Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h 24h 28h 2Ch 30h 34h 38h 3Ch MTT RC ERRCMD BUFSIZ CONFIG 40h ROUTE TCAP TMODE A4h A8h ACh B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h PMD0 PMR0 PMD1 PMR1 PME1 PMD1 PMD0 D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh
ERRSTS 44h 48h 4Ch TOM 50h LXGB HXGB HXGT 54h 58h 5Ch GAPEN MAR3 60h 64h 68h 6Ch MMBASE 70h 74h
LXGT
MAR2 MAR6
MAR1 MAR5
MAR0 MAR4
IOABASE SMRAM
PME0
MMT ISA
78h 7Ch
1. The first 64 bytes are predefined in the PCI Specification. All other locations are defined specifically for the component of interest.
3-30
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
3.4.1
BUFSIZ: Buffer Sizes
Address Offset: Default Value: 48-4Ah Size: 302308h (64-bit bus mode)Attribute: 182184h (32-bit bus mode) 24 bits Read Only
This register contains the hardwired information defining the maximum number of outbound transactions and data bytes that this PXB/PCI port can accept. Bits 23:18 Description Outbound Write Transaction Capacity. This field specifies the total number of outbound write transactions that can be accepted and queued in this PXB/PCI port. Value= 6 (32-bit bus mode) 12 (64-bit bus mode) Outbound Read Transaction Capacity. This field specifies the total number of outbound read transactions that can be accepted and queued in this PXB/PCI port. Value= 2 (32-bit bus mode) 2 (64-bit bus mode) Outbound Write Data Buffer Capacity. This field specifies the total number of data buffers available in this PXB/PCI port for use by outbound write transactions, in increments of 32 bytes. Value= 6 (x 32 bytes) (32-bit bus mode) 12 (x 32 bytes) (64-bit bus mode) Outbound Read Data Buffer Capacity. This field specifies the total number of data buffers available in this PXB/PCI port for use by outbound read transactions, in increments of 32 bytes. Value= 4 (x 32 bytes) (32-bit bus mode) 8 (x 32 bytes) (64-bit bus mode)
17:12
11:6
5:0
3.4.2
CLASS: Class Code Register
Address Offset: Default Value: Bits 23:16 09 - 0Bh 060000h Size: Attribute: 24 bits Read Only
Description Base Class For the PXB, this field is hardwired to 06h. Sub-Class For the PXB, this field is hardwired to 00h. Register-Level Programming Interface For the PXB, this field is hardwired to 00h.
15:8
7:0
Intel(R) 450NX PCIset
3-31
3. Register Descriptions
3.4.3
CLS: Cache Line Size
Address Offset: Default Value: Bits 7:0 0Ch 08h Size: Attribute: 8 bits Read/Write
Description Cache Line Size This field specifies the cache line size, in 32-bit Dword units. The Intel(R) 450NX PCIset supports only one value: 8 Dwords (32 bytes). Default=08h.
3.4.4
CONFIG: Configuration Register
Address Offset: Default Value: Bits 15 14 40-41h 2310h Size: Attribute: 16 bits Read/Write, Read-Only
Description reserved (0) PCI Bus Lock Enable. This mode works only if internal bus arbitration is selected. When set, the internal arbiter detects when the lock is established and inhibits a PCI bus grant to all agents except the agent that established the lock. Default=0. WSC# Assertion Enable. If cleared, the WSC# signal will always remain asserted. While asserted, writes continue to be accepted from the PIIX even with writes outstanding. This option is provided to allow improved performance in systems with ISA masters that desire to write to main memory. Default=1. PCI-TPA Prefetch Line Enable (PLE). If set, inbound line accesses (e.g., MRM and MRL accesses) to third-party space are treated as prefetchable. Default=0. PCI-TPA Prefetch Word Enable (PWE). If set, inbound sub-line accesses (e.g., MR accesses) to third-party space are treated as prefetchable. Default=0. Block Requests. This enable is provided for debug, diagnostic and error recovery purposes. If set, the internal arbiter ignores all further REQ[0:5]# assertions by any of the six PCI agents, and will deassert any current PCI agent's GNT# in order to prevent further inbound transactions from a parking agent. This enable has no effect if the PXB is configured to use external arbitration. Default=0. I/O Address Mask Enable. If set, on outbound I/O accesses the PXB will force A[31:16] to zero before placing the address on the PCI bus. Default=1.
13
12
11
10
9
3-32
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
8
Outbound Write Around Retried/Partial Read Enable. If set, the PXB allows outbound writes to pass retried or partially completed (i.e., disconnected) outbound reads. This enable must be set for Pentium(R) II XeonTM processor/Intel(R) 450NX PCIset systems. Default=1. Burst Write Combining Enable (BWCE). If set, back-to-back sequentially addressed outbound writes may be combined in the outbound write buffers before placement on the PCI bus. When the BWCE is cleared, all outbound write combining is disabled, and each host transaction results in a corresponding transaction on the PCI bus. Default=0. Re-streaming Buffer Enable. If set, the data returned and buffered for a Delayed Inbound Read may be re-accessed following a disconnect. If cleared, following a disconnect, the buffer is invalidated, and a subsequent read to the next location will initiate a new read. Default=0 (Disabled). Read Prefetch Size. This field configures the number of Dwords that will be prefetched on Memory Read Multiple commands. Legal values are: 00 16 Dwords (2 x 32 bytes) 10 64 Dwords (8 x 32 bytes) 01 32 Dwords (4 x 32 bytes) 11 reserved The normal selection is 32 Dwords The 64 Dword selection provides highest performance when the PXB is in 64-bit bus mode. Default=01 (32 Dwords).
7
6
5:4
3
External Arbiter Enable. This is a read-only bit that selects internal or external arbitration for the PCI bus. The bit reflects the state of the P(A,B)XARB# strapping pin for this bus (A or B). Default=[P(A,B)XARB pin]. 64-bit Bus Enable. This is a read-only bit that selects whether the PXB operates as two 32-bit PCI buses or a single 64-bit PCI bus. The bit reflects the state of the MODE64# strapping pin. Default=[MODE64# pin]. Host/PCI Bus Gearing Ratio. This is a read-only bit that selects the system clock to PCI clock gearing ratio. The bit reflects the state of the GEAR4# strapping pin. This bit should be cleared (i.e., GEAR4# is high, or deasserted), resulting in a system clock/ PCI clock gearing ratio of 3:1. Default=[GEAR4# pin]. reserved
2
1
0
3.4.5
DID: Device Identification Register
Address Offset: Default Value: 02 - 03h 84CBh Size: 16 bits Attributes: Read Only
Intel(R) 450NX PCIset
3-33
3. Register Descriptions
Bits 15:0
Description Device Identification Number. The value 84CBh indicates the Intel(R) 450NX PCIset PXB.
3.4.6
ERRCMD: Error Command Register
Address Offset: Default Value: 46h 00h Size: Attribute: 8 bits Read/Write
This register provides extended control over the assertion of SERR# beyond the basic controls specified in the PCI-standard PCICMD register. Bits 7 6 Description reserved Assert SERR# on Observed Parity Error. If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the asserting agent. Assert SERR# on Received Data with Parity Error. If set, the PXB asserts SERR# upon receiving PCI data with a parity error. This occurs regardless of whether PXB asserts it's PERR# pin. Assert SERR# on Address Parity Error. If set, the PXB asserts SERR# on detecting a PCI address parity error. Assert PERR# on Data Parity Error. If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon receiving PCI data with parity errors. Assert SERR# On Inbound Delayed Read Time-out. Each inbound read request that is accepted and serviced as a delayed read will start a watchdog timer (215 cycles). If this enable is set, the PXB will assert SERR# if the data has been returned and the timer expires before the requesting master initiates its repeat request. Default=0. Assert SERR# on Expander Bus Parity Error. If set, the PXB asserts SERR# upon detecting a parity error on packets arriving from the Expander bus. (Note that SERR# will be asserted on both PCI buses). Return Hard Fail Upon Generating Master Abort. If set, the PXB will return a Hard Fail response through the MIOC to the system bus after generating a master abort time-out for an outbound transaction placed on the PCI bus. If cleared, the PXB will return a normal response (with data of all 1's for a read). In either case, an error flag is set in the PCISTS register. Default=0.
5
4
3
2
1
0
3-34
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
3.4.7
ERRSTS: Error Status Register
Address Offset: Default Value: 44h 00h Size: Attribute: 8 bits Read/Write Clear, Sticky
This register records error conditions detected from the PCI bus (not already covered in PCISTS), from the Expander bus, and performance monitoring events. Bits remain set until explicitly cleared by software writing a 1 to the bit.
Bits 7 6
Description reserved(0) Parity Error observed on PCI Data. This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the asserting agent. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Parity Error on Received PCI Data. This flag is set if the PXB detects a parity error on data being read from the PCI bus. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Parity Error on PCI Address. This flag is set if the PXB detects a parity error on the PCI address. This flag may be configured to assert SERR# in the ERRCMD register. Inbound Delayed Read Time-out Flag. Each inbound read request that is accepted and serviced as a delayed read will initiate a watchdog timer (215 cycles). If the data has been returned and the timer expires before the requesting master initiates its repeat request, this flag will be set. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Expander Bus Parity Error Flag. This flag is set when Expander bus reports a parity error on packets received from the MIOC. This flag is set in both PCI configuration spaces. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Performance Monitor #1 Event Flag. This flag is set when the Performance Monitor #1 requests that an interrupt request be asserted. The PME and PMR registers describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted. Performance Monitor #0 Event Flag. This flag is set when the Performance Monitor #0 requests that an interrupt request be asserted. The PME and PMR registers describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted.
5
4
3
2
1
0
Intel(R) 450NX PCIset
3-35
3. Register Descriptions
3.4.8
GAPEN: Gap Enables
Address Offset: Default Value: 60h 0Eh Size: Attribute: 8 bits Read/Write
This register controls the enabling of the two programmable memory gaps, and several fixedsize/fixed-location spaces. This register applies to both host-initiated transactions and PCIinitiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.9
HDR: Header Type Register
Address Offset: Default Value: Bits 7 0Eh 00h Size: Attribute: 8 bits Read Only
Description Multi-function Device. Selects whether this is a multi-function device, that may have alternative configuration layouts. This bit is hardwired to 0. Configuration Layout. This field identifies the format of the 10h through 3Fh space. This field is hardwired to 00h, which represents the default PCI configuration layout.
6:0
3.4.10
HXGB: High Expansion Gap Base
Address Offset: Default Value: 58-5Ah 000000h Size: Attribute: 24 bits Read/Write
This register defines the starting address of the High Expansion Gap (HXG). This register applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.11
HXGT: High Expansion Gap Top
Address Offset: Default Value: 5C-5Eh 000000h Size: Attribute: 24 bits Read/Write
This register defines the highest address of the High Expansion Gap (HXG), above. HXGT applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3-36
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
3.4.12
IOABASE: I/O APIC Base Address
Address Offset: Default Value: 68-69h 0FECh Size: Attribute: 16 bits Read/Write
This register defines the base address of the 1MB I/O APIC Space address range. IOABASE applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.13
ISA: ISA Space
Address Offset: Default Value: 7Ch 00h Size: Attribute: 8 bits Read/Write
This register defines the ISA Space address range. The register applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.14
LXGB: Low Expansion Gap Base
Address Offset: Default Value: 54-55h 0000h Size: Attribute: 16 bits Read/Write
This register defines the starting address of the Low Expansion Gap (LXG). LXGB register applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.15
LXGT: Low Expansion Gap Top
Address Offset: Default Value: 56-57h 0000h Size: Attribute: 16 bits Read/Write
LXGT defines the highest address of the Low Expansion Gap (LXG), above. This register applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
Intel(R) 450NX PCIset
3-37
3. Register Descriptions
3.4.16
MAR[6:0]: Memory Attribute Region Registers
Address Offset: Default Value: 61-67h 03h for MAR[0] 00h for all others Size: Attribute: 8 bits each Read/Write
The Intel 450NX PCIset allows programmable memory attributes on 14 memory segments of various sizes in the 640 Kbyte to 1 MByte address range. Seven Memory Attribute Region (MAR) registers are used to support these features. These registers apply to both host-initiated transactions and PCI-initiated transactions, and are therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.17
MLT: Master Latency Timer Register
Address Offset: Default Value: 0Dh 00h Size: Attribute: 8 bits Read/Write
MLT is an 8-bit register that controls the amount of time (measured in PCI clocks) the Intel 450NX PCIset, as a bus master, can burst data on the PCI Bus. The Count Value is an 8 bit quantity; however, MLT[2:0] are reserved and assumed to be 0 when determining the Count Value. The number of clocks programmed in the MLT represents the guaranteed time slice allotted to the Intel 450NX PCIset, after which it must complete the current data transfer phase and then surrender the bus as soon as its bus grant is removed. Bits 7:3 Description Master Latency Timer Count Value. Counter value in 8 PCI clock units. reserved (0)
2:0
3.4.18
MMBASE: Memory-Mapped PCI Base
Address Offset: Default Value: 70-71h 0002h Size: Attribute: 16 bits Read/Write
The MMBASE register specifies the starting address of this memory-mapped PCI range, and is identical to the MMBASE register in the MIOC. The MMT register specifies the highest address that will be directed to PCI Bus #1B, and corresponds identically to the MMR[3] register in the MIOC. The MMBASE register must be programmed identically to the MMBASE register in the MIOC to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3-38
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
3.4.19
MMT: Memory-Mapped PCI Top
Address Offset: Default Value: 7A-7Bh 0001h Size: Attribute: 16 bits Read/Write
This register defines the highest address of the memory-mapped PCI space. See the MMBASE register above for a detailed description. The MMT register must be programmed identically to MMR[3] in the MIOC to achieve correct functioning.
3.4.20
MTT: Multi-Transaction Timer Register
Address Offset: Default Value: 43h 00h Size: Attribute: 8 bits Read/Write
This register controls the amount of time that the PCI bus arbiter allows a PCI initiator to perform multiple back-to-back transactions on the PCI bus. Bits 7:3 Description MTT Count Value. Specifies the guaranteed time slice (in 8-PCI-clock increments) allotted to the current agent, after which the PXB will grant the bus as soon as other PCI masters request the bus. A value of 0 disables this function. Default=0. reserved (0)
2:0
3.4.21
PCICMD: PCI Command Register
Address Offset: Default Value: 04 - 05h 0016h Size: Attribute: 16 bits Read/Write, Read-Only
This is a PCI specification required register with a fixed format. Bits 15:10 9 Description reserved (0) Fast Back-to-Back. Fast back-to-back cycles are not implemented by the PXB, and this bit is hardwired to 0. SERR# Enable (SERRE). If this bit is set, the PXB's SERR# signal driver is enabled and SERR# is asserted for all relevant bits set in the ERRSTS and PCISTS as controlled by the corresponding bits of the ERRCMD register. If SERRE is set and the PXB's PCI parity error reporting is enabled by the PERRE bit, then the PXB will assert SERR# on address parity errors. Default=0.
8
Intel(R) 450NX PCIset
3-39
3. Register Descriptions
7
Address/Data Stepping. The PXB does not support address/data stepping, and this bit is hardwired to 0. Parity Error Response (PERRE). If PERRE is set, the PXB will report parity errors on data received by asserting the PERR# signal. Address parity errors are not reported using PERR#, but instead through the SERR# signal, and only if both PERRE and SERRE are set. If PERRE is cleared, then PCI parity errors are not reported by the PXB. Default=0. reserved (0) Memory Write and Invalidate Enable. Selects whether the PXB, as a PCI master, can generate Memory Write and Invalidate cycles. Default=1. Special Cycle Enable. The PXB will ignore all special cycles generated on the PCI bus, and this bit is hardwired to 0. Bus Master Enable. The PXB does not permit disabling of its bus master capability, and this bit is hardwired to 1. Memory Access Enable. The PXB does not permit disabling access to main memory, and this bit is hardwired to 1. I/O Access Enable. The PXB does not respond to PCI I/O cycles, and this bit is hardwired to 0.
6
5 4
3
2
1
0
3.4.22
PCISTS: PCI Status Register
Address Offset: Default Value: 06 - 07h 0280h Size: Attribute: 16 bits Read/Write Clear, Sticky
This is a PCI specification required register, with a fixed format. Bits 15 Description Parity Error (PE). This bit is set when the PXB detects a parity error in data or address on the PCI bus. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Signaled System Error (SSE). This bit is set when the PXB asserts the SERR# signal. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0.
14
3-40
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
13
Received Master Abort (RMA). This bit is set when the PXB, as bus master, terminates its transaction (except for Special Cycles) with a master abort. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Received Target Abort (RTA). This bit is set when the PXB, as bus master, receives a target abort for its transaction. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Signaled Target Abort (STA). This bit is set when the PXB, as bus target, terminates a transaction with target abort. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. DEVSEL# Timing (DEVT). This 2-bit field encodes the timing of the DEVSEL# signal when the PXB responds as a target, and represents the slowest time that the PXB asserts DEVSEL# for any bus command except Configuration Reads or Writes. This field is hardwired to the value 01b (medium). Data Parity Error (DPE). This bit is set when all of the following conditions are met: 1. The PXB asserted PERR# or sampled PERR# asserted. 2. The PXB was the initiator for the operation in which the error occurred. 3. The PERRE bit in the PCICMD register is set. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Fast Back-to-Back (FB2B). The PXB supports fast back-to-back transactions, and this bit is hardwired to 1. UDF Supported. The PXB does not support User Definable Features (UDF), and this bit is hardwired to 0. 66 MHz Capable. The PXB is not capable of running at 66 MHz, and this bit is hardwired to 0. reserved (0)
12
11
10:9
8
7
6
5
4:0
3.4.23
PMD[1:0]: Performance Monitoring Data Register
Address Offset: Default Value: D8-DCh, E0-E4h 000000000000h each Size: Attribute: 40 bits each Read/Write
Two performance monitoring counters, with associated event selection and control registers, are provided for each PCI bus in the PXB. The PMD registers hold the performance monitoring count values. Event selection is controlled by the PME registers, and the action performed on event detection is controlled by the PMR registers.
Intel(R) 450NX PCIset
3-41
3. Register Descriptions
Bits 39:0
Description Count Value.
3.4.24
PME[1:0]: Performance Monitoring Event Selection
Address Offset: Default Value: Bits 15 14 E8 - EBh 0000h each Size: Attribute: 16 bits each Read/Write
Description reserved (0) Count Data Cycles 1: Count the data cycles associated with the selected transactions. 0: Count the selected event Initiating Agent Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions issued by specific agents. 0000 Agent 0 1000 reserved 0001 Agent 1 1001 reserved 0010 Agent 2 1010 reserved 0011 Agent 3 1011 reserved 0100 Agent 4 1100 reserved 0101 Agent 5 1101 south bridge 0110 reserved 1110 Intel(R) 450NX PCIset agent (i.e., outbound) 0111 reserved 1111 Any agent Note: This field is applicable only if the PCI bus is operated in internal arbiter mode. If the bus is operated using an external arbiter, this field must be set to Any Agent to trigger any events.
13:10
9:8
Transaction Destination Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions directed to a specific resource. 00 Any 10 PCI Target 01 Main Memory 11 Third party reserved
7:6
3-42
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
5:0
Event Selection. This field specifies the basic PCI bus transaction or PCI bus signal to be monitored. Individual Bus Transactions 00 0000 reserved 00 1000 reserved 00 0001 reserved 00 1001 reserved 00 0010 I/O Read 00 1010 reserved 00 0011 I/O Write 00 1011 reserved 00 0100 reserved 00 1100 Memory Read Multiple 00 0101 reserved 00 1101 Dual Address Cycle 00 0110 Memory Read 00 1110 Memory Read Line 00 0111 Memory Write 00 1111 Memory Write & Invalidate
Generic (Grouped) Bus Transactions 010 000 Any bus transaction 010 001 Any memory transaction 010 010 Any memory read 010 011 Any memory write Bus Signal Assertions 011 000 reserved 011 001 reserved 011 010 RETRY1 011 011 reserved All other encodings are reserved.
010 100 010 101 010 110 010 111 011 100 011 101 011 110 011 111
Any I/O transaction Any I/O or memory transactions Any I/O read or memory read Any I/O read or memory write reserved reserved LOCK ACK64
Note: 1. Counting data cycles is undefined for this selection.
3.4.25
PMR[1:0]: Performance Monitoring Response
Address Offset: Default Value: DDh, E5h 0000h each Size: Attribute: 8 bits each Read/Write
There are two PMR registers for each PCI bus, one for each PMD counter. Each PMR register specifies how the event selected by the corresponding PME register affects the associated PMD register, P(A,B)MON# pins, and the INT(A,B)RQ# pins. Bits 7:6 Description Interrupt Assertion Defines how selected event affects INTRQ# assertion. Whenever INTRQ# is asserted, a flag for this counter is set in the Error Status Register, so that software can determine the cause of the interrupt. This flag is reset by writing the Error Status Register. 0 Selected event does not assert INTRQ # reserved 1 2 Assert INTRQ# pin when event occurs 3 Assert INTRQ# pin when counter overflows Performance Monitoring pin assertion Defines how the selected event affects the PMON# pin for this counter. PMON# pin is tristated. Selected event has no effect. 0 reserved 1
5:4
Intel(R) 450NX PCIset
3-43
3. Register Descriptions
2 3 3:2
Assert this counter's PMON# pin when event occurs Assert this counter's PMON# pin when counter overflows
Count Mode Selects when the counter is updated for the detected event. 0 Stop counting. 1 Count each cycle selected event is active. 2 Count on each rising edge of the selected event. 3 Trigger. Start counting on the first rising edge of the selected event, and continue counting each clock cycle. Reload Mode Reload has priority over increment. That is, if a reload event and a count event happen simultaneously, the count event has no effect. 0 Never reload 1 Reload when this counter overflows. 2 Reload when the other counter overflows. 3 Reload unless the other counter increments.
1:0
3.4.26
RID: Revision Identification Register
Address Offset: Default Value: Bits 7:0 08h 00h Size: Attribute: 8 bits Read Only
Description Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the PXB. These bits are read only and writes to this register have no effect.
3.4.27
RC: Reset Control Register
Address Offset: Default Value: 47h 01h Size: Attribute: 8 bits Read/Write/Sticky
The RC register controls the response of the PXB to XRST#. Bits 7:1 0 Description reserved (0) Reset PCI clocks on XRST# Clearing this bit enables PCICLKA and PCICLKB to run undisturbed through reset. When set, PCI clock phase will be reset whenever XRST# is asserted. When clear, System Hard Resets, PXB Resets, Soft Resets, BINIT Resets will not disturb PCICLKA and PCICLKB. This bit is defined to be sticky so that it can only be modified by PWRGD or configuration write. Default=1.
3-44
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
3.4.28
ROUTE: Route Field Seed
Address Offset: Default Value: C3h 73h (A-side space) 62h (B-side space) Size: Attribute: 8 bits Read/Write
Bits 7:4
Description Inbound-to-Host-Bus Route Seed. This field represents the "seed" value used to create the routing field for packets inbound to the system bus (i.e., third-party). 0111b Default: (A-side configuration space) 0110b (B-side configuration space) Inbound-to-Memory Route Seed. This field represents the "seed" value used to create the routing field for packets inbound to memory. 0011b Default: (A-side configuration space) 0010b (B-side configuration space)
3:0
3.4.29
SMRAM: SMM RAM Control Register
Address Offset: Default Value: 6C-6Fh 00000Ah Size: Attribute: 32 bits Read/Write
This register defines the System Management Mode RAM address range, and enables the control access into that range. Fields of this register which exist in the MIOC SMRAM register must be programmed to the same values. Bits 31 Description SMRAM Enable (SMRAME). If set, the SMRAM space is protected from inbound PCI bus access. If clear, this register has no effect on inbound memory accesses. Default=0. reserved (0) SMM Space Size. This field specifies the size of the SMM RAM space, in 64 KB increments. 0h 4h 320 KB 8h 576 KB Ch 832 KB 64 KB 1h 128 KB 5h 384 KB 9h 640 KB Dh 896 KB 2h 192 KB 6h 448 KB Ah 704 KB Eh 960 KB 3h 256 KB 7h 512 KB Bh 768 KB Fh 1 MB Default: 0h (64 KB). 19:16 15:0 reserved (0) SMM Space Base Address. This field specifies the A[31:16] portion of the SMM RAM space base address (A[15:0]=0000h). The space may be relocated anywhere below the 4 GB boundary
30:24 23:20
Intel(R) 450NX PCIset
3-45
3. Register Descriptions
and the Top of Memory (TOM); however, the base address must be aligned on the next highest power-of-2 natural boundary given the chosen size. Incorrect alignment results in indeterminate operation. Default: 000Ah (representing a base address of A0000h)
3.4.30
TCAP: Target Capacity
Address Offset: Default Value: C0-C2h 041082h Size: Attribute: 24 bits Read/Write
This register is programmed with the maximum number of transactions and data bytes that the receiving MIOC can accept from this PXB/PCI port for inbound transactions. The MIOC space has a set of four similar TCAP registers, one per PXB/PCI bus, that is programmed with the transaction and data limits for outbound transactions. If the PXB is in 32-bit bus mode, divide the MIOC BUFSIZ limits in half. If the PXB is in 64-bit bus mode, the full MIOC BUFSIZ limits can be used, except in either case, the PXB's maximum values (shown below) cannot be exceeded. Bits 23:18 Description Inbound Write Transaction Capacity. This field specifies the total number of inbound write transactions that can be forwarded and enqueued in the MIOC from this PXB/PCI port. 32-bit Bus PXB maximum: 6 Minimum allowed: 1 Default= 1 64-bit Bus PXB maximum: 12 Minimum allowed: 1 Default= 1 Inbound Read Transaction Capacity. This field specifies the total number of inbound read transactions that can be forwarded and enqueued in the MIOC from this PXB/PCI port. 32-bit Bus PXB maximum: 2 Minimum allowed: 1 Default= 1 64-bit Bus PXB maximum: 2 Minimum allowed: 1 Default= 1 Inbound Write Data Buffer Capacity. This field specifies the total number of data buffers available in the MIOC for use by inbound write transactions from this PXB/PCI port, in increments of 32 bytes. 32-bit Bus PXB maximum: 6 Minimum allowed: 2 Default= 2 64-bit Bus PXB maximum: 12 Minimum allowed: 2 Default= 2 Inbound Read Data Buffer Capacity. This field specifies the total number of data buffers available in the MIOC for use by inbound read transactions from this PXB/PCI port, in increments of 32 bytes. 32-bit Bus PXB maximum: 8 Minimum allowed: 2 Default= 2 64-bit Bus PXB maximum: 16 Minimum allowed: 2 Default= 2
17:12
11:6
5:0
3.4.31
TMODE: Timer Mode
Address Offset: Default Value: C4h 00h Size: Attribute: 8 bits Read/Write
3-46
Intel(R) 450NX PCIset
3.4 PXB Configuration Space
This register allows nominally fixed-duration timers to be adjusted to shorter values for test purposes. Bits 7:2 1:0 Description reserved (0) Delayed Read Request Expiration Counter. This counter is strictly for test purposes. Changing it from the default value is a violation of the PCI specification. 00 normal mode (215 clocks) 01 128 clocks 10 64 clocks 11 16 clocks
3.4.32
TOM: Top of Memory
Address Offset: Default Value: 50-52h 000FFFh Size: Attribute: 24 bits Read/Write
This register specifies the highest physical address that could be directed to the memory. This register applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.33
VID: Vendor Identification Register
Address Offset: Default Value: Bits 15:0 00 - 01h 8086h Size: 16 bits Attributes: Read Only
Description Vendor Identification Number. This is a 16-bit value assigned to Intel.
Intel VID = 8086h.
Intel(R) 450NX PCIset
3-47
3. Register Descriptions
3-48
Intel(R) 450NX PCIset
System Address Maps
4
4.1
Memory Address Map
A Pentium(R) II XeonTM processor system based on the Intel(R) 450NX PCIset supports up to 64 GBytes of addressable memory space. Within this memory address range the Intel 450NX PCIset has two structured compatibility regions, two expansion gaps, and two general purpose memory-mapped I/O spaces, as illustrated in Figure 4-1. The two compatibility regions are the 1 MB Low Compatibility Region at the bottom of the address space, and the 20 MB High Compatibility Region just below the 4 GB boundary. The two expansion gaps allow holes to be opened in the address space, where accesses can be directed to the PCI buses or to a third-party agent, instead of to memory. The two I/O spaces allow control over which addresses are forwarded to each of the four PCI buses supported by the Intel 450NX PCIset.
Spaces and Gaps
The Intel 450NX PCIset memory address map is based on spaces and gaps. A space is an address range where the access is directed to a specific destination, usually (but not always) a PCI bus. Any DRAM behind the space is not reclaimed, unless it is also covered by a gap (described below). The Intel 450NX PCIset supports a variety of spaces with fixed or configurable address ranges and individual enables. A gap is a memory-mapped address range where the access is specifically not directed to DRAM. The DRAM behind the gap is reclaimed; that is, the effective address presented to the memory has the gaps subtracted from it, presenting a contiguous address space to the memory. The gap does not control where the access is directed. Accesses may be directed through an overlapping space, or left unclaimed on the system bus for a third-party agent to claim. In typical maps, large spaces will be contained within gaps, to reclaim the DRAM that would otherwise be wasted. The Intel 450NX PCIset supports two configurable gaps.
Low Compatibility Region
The Low Compatibility Region spans the first 1 MB address range (0h to F_FFFFh). This region is divided into five subregions, some of which are further subdivided. * * The 640 KB DOS Region is split into a 512 KB DOS area (memory only) and a 128 KB ISA Window, which can be mapped to either main memory or the PCI memory. The 128 KB Graphics Adapter Memory is normally mapped to a video device on the PCI bus, typically a VGA controller. This region is also the default location of the configuration SMM RAM space.
Intel(R) 450NX PCIset
4-1
4. System Address Maps
F_FFFF_FFFF
64 GB 20 MB Total
High BIOS
FFE0_0000
2 MB 14 MB
1_0000_0000
FEF0_0000
Local APIC
Top of Memory
1 MB 1 MB 1 MB 1 MB
High Compatibility Region
4 GB
FEE0_0000 FEC0_0000
Reserved
I/O APIC
Local PCI Bus 1b Local PCI Bus 1a Local PCI Bus 0b Local PCI Bus 0a
High Expansion Gap
100_0000
16 MB
Low ISA Space
Low Expansion Gap
10_0000
0
Low Compatibility Region
1 MB
F_0000 E_0000 C_0000 A_0000
System BIOS
64K C_8000 Channel I/O
Ext System BIOS 64K ISA Expansion
128K
ISA
96KB
Video BIOS 32KB
Graphics Adapter 128K Memory
8_0000
ISA Window 128KB DOS Area
512KB
Areas are not drawn to scale. 0
DOS Region
640K
Figure 4-1: *
System Memory Address Space
The 128 KB ISA Expansion Region is divided into eight 16 KB blocks that can be independently configured for read/write accessibility. Typically, these blocks are mapped through the PCI bridge to ISA space. Memory that is disabled is not remapped. Traditionally, the lower 32 KB contains the video BIOS located on a video card, and the upper 96 KB is made available to expand memory windows in 16 KB blocks depending on the requirements of other channel devices in the corresponding ISA space. The 64 KB Extended System BIOS Region is divided into four 16 KB blocks and may be mapped either to memory or the compatibility PCI bus. Typically, this area is used for RAM or ROM. Selecting appropriate read/write attributes for this region allows the BIOS to be "shadowed" into RAM.
*
4-2
Intel(R) 450NX PCIset
4.1 Memory Address Map
Top Of Memory
High Gap
PCI space
Low Gap
wasted
ISA space

Physical Memory
Host Bus Address
Figure 4-2:
Gaps, Spaces and Reclaiming Physical Memory
*
The 64 KB System BIOS Region is treated as a single block and is normally mapped to the compatibility PCI bus. Selecting appropriate read/write attributes for this region allows the BIOS to be "shadowed" into RAM. After power-on reset, the Intel(R) 450NX PCIset has this area configured to direct accesses to PCI memory, allowing fetches from the boot ROM during system initialization.
High Compatibility Region
The High Compatibility Region spans 20 MB immediately below the 4 GB address boundary (address range FEC0_0000h to FFFF_FFFFh). This region supports four fixed spaces with predefined functions for compatibility with PC-based systems. * The 2 MB High BIOS Space is where the processor begins execution after reset. Following power-on, the Intel(R) 450NX PCIset has this space enabled; accesses will be directed to the compatibility PCI bus. If an ISA bridge is also used, this area is then aliased by the ISA bridge to the top of the ISA address range (14-16 MB). If this space is disabled, accesses will be directed to memory (unless superceded by an expansion gap.) The 1 MB Local APIC Space is reserved for use by the processor. In Pentium(R) II XeonTM processors, this contains the default local APIC space (which can be remapped to the I/O APIC space, below). Accesses to this region will not be claimed by the Intel 450NX PCIset. No resources should be mapped to this region. The 1 MB Reserved Space is defined for future use. No resources should be mapped to this region. The 1 MB I/O APIC Configuration Space provides an area where I/O APIC units in the system can be mapped, and the I/O APICs within the processors can be remapped for consistency of access. At least one I/O APIC must be included in an Intel 450NX PCIsetbased system. The I/O APIC space may be relocated anywhere in the 4 GB boundary.
*
* *
Intel(R) 450NX PCIset
4-3
4. System Address Maps
Top of Memory and Expansion Gaps
A "Top of Memory" pointer identifies the highest memory-mapped address that can be serviced by this node. Accesses to addresses above this pointer will not be directed to local memory or the PCI buses, but will be allowed to sit unclaimed on the system bus. A thirdparty agent on the system bus may claim such accesses, either servicing them with its own local resources or forwarding them to other nodes for service (i.e., a cluster bridge). Any access that remains unclaimed will eventually timeout in the Intel 450NX PCIset; on timeout the access is claimed by the Intel 450NX PCIset and terminated. Below the Top of Memory, there are two programmable expansion gaps: the Low Expansion Gap and the High Expansion Gap. Each gap, if enabled, opens a "hole" in the physical address space, where accesses will not be directed to memory. Instead, these accesses may be directed to one of the PCI buses, or will be allowed to sit unclaimed on the system bus where they may be claimed by a third-party agent, as above. Both expansion gaps are defined using base and top addresses, on 1MB boundaries. The Low Expansion Gap must be located above the Low Compatibility Region, and below the High Expansion Gap, the 4 GB boundary, and the Top of Memory. The High Expansion Gap must be located above the enabled Low Expansion Gap, above 1MB, and below the Top of Memory. At power-on, both gaps are disabled.
4.1.1
Memory-Mapped I/O Spaces
The Intel(R) 450NX PCIset provides two programmable I/O spaces: the Low ISA Space and the PCI Space. Both spaces allow accesses to be directed to a PCI bus. Any region defined as memory-mapped I/O must have a UC (UnCacheable) memory type, set in the Pentium II Xeon processor's MTTR registers.
Low ISA Space
The Low ISA Space is provided to support older ISA devices which cannot be relocated above the 16 MB address limit of older systems. Accesses to this space will be directed down to the compatibility PCI bus (0A). The Low ISA Space can start on any 1 MB boundary below 16 MB, and can be of size 1, 2, 4 or 8 MB.
PCI Space
The PCI Space consists of four contiguous address ranges, allowing accesses to be directed to each of the four PCI buses supported by the Intel 450NX PCIset. Each address range corresponds to a PCI bus, and is configurable on 1 MB boundaries.
4.1.2
SMM RAM Support
Intel Architecture processors include a System Management Mode (SMM) that defines a protected region of memory called SM RAM. The Intel 450NX PCIset allows an SM RAM region to be defined and enabled. When enabled, memory reads and writes to addresses that fall within the SM RAM address range are protected accesses. If the configuration enables permit access, and the requesting agent asserts SMMEM# (priveleged access), the MIOC will
4-4
Intel(R) 450NX PCIset
4.2 I/O Space
direct the access to DRAM. Otherwise, the access will be forwarded to the compatibility PCI bus. If SMM is not enabled in the Intel 450NX PCIset, accesses are treated normally.
4.2
I/O Space
The Intel(R) 450NX PCIset allows I/O accesses to be mapped to resources supported on any of the four PCI buses. The 64KB I/O address range is partitioned into sixteen 4 KB segments which may be partitioned amongst the four PCI buses, as shown in Figure 4-3. Host-initiated accesses that fall within a bus' I/O range are directed to that bus. Segment 0 always defaults to the compatibility PCI bus. The Intel 450NX PCIset's I/O Range Register defines the mapping of I/O segments to each PCI bus. This is illustrated in Figure 4-3. Accesses that fall within an I/O address range and forwarded to the selected PCI bus, but not claimed by a device on that bus, will time-out and be terminated by the Intel 450NX PCIset.
I/O Space Mapping to PCI Buses FFFF F000 Segment 15 I/O Space Bus 1B IOR.BUS1A (top) FFFF Segment Configuration
ISA Alias Mode Disabled ISA Alias Mode Enabled
xFFF xD00 xC00 x900 x800 x500 x400 x100 x000 IOR.BUS0A (top)
xFFF xD00 xC00 x900 x800 x500 x400 x100 x000
I/O Space Bus 1A 4000 Segment 3 Segment 2 Segment 1 Segment 0 I/O Space Bus 0A I/O Space Bus 0B
IOR.BUS0B (top)
3000
2000
Segment 0
1000
03FF 0100 0000
0000
0000
Figure 4-3:
I/O Space Address Mapping
The Intel 450NX PCIset optionally supports ISA expansion aliasing, as shown in Figure 4-3. When ISA expansion aliasing is supported, the ranges designated as I/O Expansion are internally aliased to the 0100h-03FFh range in Segment 0 before the normal I/O address range checking is performed. This aliasing is only for purposes of routing to the correct PCI bus. The address that appears on the PCI bus is unaltered. ISA expansion aliasing is enabled or disabled through the ISA Aliasing Enable bit in the MIOC's CONFIG register.
Intel(R) 450NX PCIset
4-5
4. System Address Maps
Restricted-Access Addresses
By default, all Host-PCI I/O writes will be posted. However, in traditional Intel-architecture systems, there are certain I/O addresses to which posting is not desirable, due to ordering side effects. Table 4-1 lists the I/O addresses for which I/O write posting will not be supported, regardless of the posting enable in the MIOC's CONFIG register. These accesses will be deferred instead. Table 4-1: Non-Postable I/O Addresses Address 0020h-0021h 0060h-0064h 0070h 0092h 00A0h-00A1h 00F0h 0CF8h, 0CFCh Function 8259A Interrupt Controller, Master, Interrupt Masks Keyboard controller: com/status and data NMI# Mask A20 Gate 8259A Interrupt Controller, Slave, Interrupt Masks IGNNE#, IRQ13 PCI configuration space access
4.3
PCI Configuration Space
The Intel(R) 450NX PCIset provides a PCI-compatible configuration space for the MIOC, and two in the PXB--one for each PCI bus. I/O reads and writes issued on the system bus are normally claimed by the MIOC and forwarded through the PXBs as I/O reads and writes on the PCI bus. However, I/O accesses to the 0CF8h and 0CFCh addresses are defined as special configuration accesses for I/O devices. Each configuration space is selected using a Bus Number and a Device Number within that bus. PCI buses are numbered in ascending order within hierarchical buses. PCI Bus #0 represents both the compatibility PCI bus as well as the devices in the Intel 450NX PCIset and any third party agents attached to the system bus. The MIOC and each PCI bus within each PXB in the system is assigned a unique Device Number on Bus #0, as shown in Table 4-2. The PXBs are numbered based on the Expander bus port used. Table 4-2: Device Numbers for Bus Number 0 1 2 Device Number 10h 11h 12h 13h MIOC reserved PXB 0, Bus a PXB 0, Bus b
3
Device
Device Number 18h 19h 1Ah 1Bh
Device
4-6
Intel(R) 450NX PCIset
4.3 PCI Configuration Space
Table 4-2: Device Numbers for Bus Number 0 (Continued)1 2 Device Number 14h 15h 16h 17h Device PXB 1, Bus a PXB 1, Bus b Device Number 1Ch 1Dh 1Eh 1Fh Device Third Party Agent Third Party Agent Third Party Agent n/a 4
1. Device numbers 0-15 represent devices actually on the compatibility PCI bus. 2. Shaded columns are defined for future PCIset compatibility. 3. This is the compatibility PCI bus. 4. Bus #0/Device # 31 is used (along with a Function Number of all 1's and a Register Number of all 0's) to generate a PCI Special Cycle. Therefore Bus #0/Device #31 is never mapped to a device.
Intel(R) 450NX PCIset
4-7
4. System Address Maps
4-8
Intel(R) 450NX PCIset
Interfaces
5
5.1
System Bus
The host interface of the Intel(R) 450NX PCIset is targeted toward Pentium(R) II XeonTM processor-based multiprocessor systems, and is specifically optimized for four processors sharing a common bus with bus clock frequencies of 100 MHz. The MIOC provides the system bus address, control and data interfaces for the Intel 450NX PCIset, and represents a single electrical load on the system bus. The Intel 450NX PCIset recognizes and supports a large subset of the transaction types that are defined for the P6 family processor's bus interface. However, each of these transaction types have a multitude of response types, some of which are not supported by this controller. The responses that are supported by the MIOC are: Normal without Data, Normal with Data, Retry, Implicit Write Back, Deferred Response. Refer to the chapter on Transactions for more details on the transaction types supported by the Intel 450NX PCIset.
5.2
PCI Bus
Each PXB provides two independent 32-bit, 33 MHz Rev. 2.1-compliant PCI interfaces which support 5 volt or 3 volt PCI devices. Each bus will support up to 10 electrical loads, where the PXB and the PIIX4E south bridge each represent one load, and each connector/device pair represents two loads. The internal bus arbiter supports six PCI bus masters in addition to the PXB itself and the south bridge on the compatibility bus. The compatibility bus is always bus #0A (PXB #0, Bus A). The PCI buses are operated synchronously with the system bus, using the system bus clock as the master clock. A system bus/PCI bus clock ratio of 3:1 supports the Intel Pentium (R) II XeonTM processor at 100 MHz with 33.3 MHz PCI bus, or a degraded 90 MHz system bus with a 30 MHz PCI bus (or lower, depending on the effect of the 6th load on the system bus). A configuration option allows the two 32-bit PCI buses (A and B) on a single PXB to be operated in combination as a single 64-bit PCI bus. Bus A data represents the low Dword, while bus B data represents the high Dword.
5.3
Expander Bus
The Expander Interface provides a bidirectional path for data and control between the PXB and MIOC components. The Expander bus consists of a 16 bit wide data bus which carries command, address, data, and transaction information. There are two additional bits that carry
Intel(R) 450NX PCIset
5-1
5. Interfaces
Byte enable information for data fields. All 18 of these bits are protected by an even parity signal. Two synchronous arbitration signals (one in each direction) are used for each Expander bus.
5.3.1
Expander Electrical Signal and Clock Distribution
The Expander bus is designed to allow multiple high bandwidth I/O ports to be added to the Intel(R) 450NX PCIset with minimal impact on signal pin count. The Expander bus also provides flexibility in server system topology by allowing the I/O subsystem to be located away from the main PCIset. This flexibility is achieved with a signaling scheme that uses a combination of synchronous and source synchronous clocking. This is illustrated in Figure 51.
Expander Bus MIOC
HRTS# XRTS# XADS# XBE[1:0] XD[15:0] XPAR HSTBP# Strobe Synch HSTBN# XSTBP# XSTBN# XRSTFB# XRSTB# XRST# XCLK XCLKB XCLKFB Strobe Synch
PXB
PXB RST
R PLL FB R PLL FB
(L1) (L2) (L3) (L4)
HCLKIN
Required length matching: L1=L2=L3=L4
Core CLK
Figure 5-1:
Expander Bus Clock Distribution
5.4
Third-Party Agents
In addition to the processors and the Intel(R) 450NX PCIset, the Pentium(R) II XeonTM processor bus allows for additional bus masters, generically referred to as third-party agents (TPA). These agents may be symmetric agents, in which case they must participate in the bus arbitration algorithm used by the processors. They may also be priority agents, in which case they must negotiate with the Intel 450NX PCIset for control of the system bus.
5-2
Intel(R) 450NX PCIset
5.5 Connectors
The Intel 450NX PCIset supports the same request/grant and third-party control signals originally provided by the Intel 450GX PCIset. Theses signals are used to exchange priority ownership of the bus between the TPA and the Intel 450NX PCIset. The Intel 450NX PCIset makes no assumptions about the relative priorities between the Intel 450NX PCIset and the TPA, and will grant priority ownership at the next natural transaction boundary. The Intel 450NX PCIset also makes no assumptions about the frequency of TPA requests or the duration of TPA bus ownership; it is the responsibility of the TPA to ensure that its use of the system bus is commensurate with its intended purpose and expected system performance.
5.5
Connectors
Connectors are permitted only for the memory cards and between the MIOC and PXBs. Between MIOC and PXB, some degree of "stretch" distance is possible, with specific distance dependent on the design and medium chosen. Connectors are specifically not permitted between the MIOC and the system bus.
Intel(R) 450NX PCIset
5-3
5. Interfaces
5-4
Intel(R) 450NX PCIset
Memory Subsystem
6
6.1
Overview
The Intel 450NX(R) PCIset's memory subsystem consists of one or two memory cards. Each card is comprised of one RCG component, a DRAM array, and two MUX components. Table 6-1 summarizes the Intel 450NX PCIset's general memory characteristics. Table 6-1: General Memory Characteristics DRAM type Memory modules DRAM technologies Extended Data Out (EDO) 72-bit, single and double high DIMMs 16 Mbit and 64 Mbit 50 and 60 nsec 3.3 V 4:1, 2:1 (in bank 0, of card 0) 2:1 interleave: 32 MB 4:1 interleave: 64 MB to 8 GB, in 64 MB increments
Interleaves Memory size
6.1.1
Physical Organization
The Intel(R) 450NX PCIset supports up to 8 banks of memory, configured across one or two memory cards. Each bank can support up to 1 GB using 64 Mbit double-high DIMMs to provide a total of 8 GB of memory in 8 banks. Each bank can support one or two rows of 2 or 4 interleaves. Each row represents a set of memory devices simultaneously selected by a RAS# signal. Each interleave generates 72 bits (64 data, 8 ECC) of data per row using one DIMM. Four interleaves provide a total of 256 bits of data (32 bytes) which is one cache line for the Pentium(R) II XeonTM processor. Data from multiple interleaves are combined by the MUXs to exchange 72 bits of data with the MIOC at an effective rate of one cache line every 30ns (effective rate: 1.067 GB/s) for a 4-way interleaved memory. Figure 6-1 illustrates this configuration.
The RCG and MUX Components
The RCGs generate the signals to control accesses to the main memory DRAMs. The RCG initiates no activity until it receives a command from the MIOC. The maximum number of RCGs per Intel 450NX PCIset system is two. Each RCG controls up to four banks of DRAM. Each bank of memory may consist of one (for single-sided DIMMs) or two (for double-sided or double-high DIMMs) rows. Internally, each RCG component contains four RAS/CAS control units (RCCUs), each dedicated to one bank of DRAM. This is illustrated in Figure 6-2. Each MUX component has four 36-bit data I/O connections to DRAM (one 18-bit path for each of four possible interleaved quad-words) and one 36-bit data I/O connection to the MD
Intel(R) 450NX PCIset
6-1
6. Memory Subsystem
Pentium(R) II XeonTM processor system bus addr[35:0], data[71:0] & ctrls
MD[71:0] 2x36 72 36 36
memory cards
MUXs
MIOC
Memory Control Interface
RCG
rows bank Card 1
to PCI via Expander bridge
Card 0
Figure 6-1:
Memory Configuration Using 2 Cards
To/From MIOC CMND[1:0] CSTB# REQ_SEL[5:0}# MA[13:0]#
Memory Array
RCMPLT# RASA[a:d][1:0]#, CASA[a:d][1:0]#, WEA[a:b]# ADDRA[13:0] Bank A RASB[a:d][1:0]#, CASB[a:d][1:0]#, WEB[a:b]# ADDRB[13:0] Bank B RCG #0 RASC[a:d][1:0]#, CASC[a:d][1:0]#, WEC[a:b]# ADDRC[13:0] Bank C RASD[a:d][1:0]#, CASD[a:d][1:0]#, WED[a:b]#
GRCMPLT#
ADDRD[13:0] Bank D AVWP# LDSTB# LRD# WDME# GDCMPLT# To/From Other MUXs
MUXs (2) DOFF[1:0]# DSEL# DVALID[a:b]# WDEVT# From MIOC DCMPLT[a:b]# DSTBP[3:0]# DSTBN[3:0]#
To/From Other RCGs
To/From MIOC
Figure 6-2:
Example Showing RCG/MUX Control Signals
6-2
Intel(R) 450NX PCIset
6.1 Overview
bus. There are two MUX components per board to provide a 72-bit data path from each of four possible interleaved quad-words to the MD bus. This is illustrated in Figure 6-3.
QD0[71:36] QD1[71:36] QD2[71:36] QD3[71:36]
Memory Card
MUX
DSTBP[3:2]#, DSTBN[3:2]#
MD[71:36]
MD[71:0] DSTBP[3:0]#, DSTBN[3:0]#
To MIOC
DSTBP[1:0]#, DSTBN[1:0]# To other memory card
Figure 6-3:
Memory Card Datapath
6.1.2
Configuration Rules and Limitations
Memory array configurations are governed by the following rules: * * * * * * * Either one or two cards can be populated in a working system. Any number of memory rows, on either card, can be populated in a working system. Memory banks can be populated in any order on either card. Cards designed to support 4:1 interleaving will also support 2:1 interleaves (in the first bank only). Within any given row, the populated interleaves must have DIMMs of uniform size. Memory sizes (16 MB vs. 64 MB) may be mixed within a memory card, but must be the same within a bank. Memory speeds (60ns or faster) may be mixed, but all four banks within an RCG operate at the same speed, and must therefore be configured to the slowest DIMM in the set.
6.1.2.1
Interleaving The Intel 450NX PCIset supports 4:1 interleaving across all banks, and 2:1 interleaving in the first bank of card #0 only. The Intel 450NX PCIset does not support non-interleaved configurations. Interleave configuration register programming must be consistent across the entire memory system. For example, if one bank is configured as 4:1 then the entire memory sub-system must be 4:1 and the associated memory bank configuration registers must be programmed as 4:1. To support a 4:1 interleave requires two MUXs. Supporting a 2:1 interleave requires only one MUX. A two-MUX design will also support 2:1 interleaves. An entry-level card (i.e., 2:1
MD[35:0]
QD0[35:0] QD1[35:0] QD2[35:0] QD3[35:0]
MUX
Intel(R) 450NX PCIset
6-3
6. Memory Subsystem
interleave) that may be expanded beyond the first bank must therefore be designed using two MUXs. Table 6-2 gives a summary of the characteristics of memory configurations supported by the Intel 450NX PCIset for 4-way interleaved memory cards. Table 6-2: Minimum and Maximum Memory Size Per Card Addressing DRAM Technology & Config. DIMM Size Memory Size for 4-way Interleave Max (Doublehigh DIMMs) 512 MB 1 GB 2 GB 4 GB
Mode
Size row/col
Min (DIMMs)
Max (DIMMs)
16M
2M x 8 4M x 4
2M x 72 Asymmetric 4M x72 Symmetric Asymmetric 8M x 72 Asymmetric 16M x 72 Symmetric Asymmetric
11 11 12 12 12 13
10 11 10 11 12 11
64 MB 128 MB 256 MB 512 MB
256 MB 512 MB 1 GB 2 GB
64M
8M x 8 16M x 4
6.1.2.2
Address Bit Permuting Rules and Limitations The Intel 450NX PCIset supports permuting of cache lines across two or four populated banks. For a complete description of the operation of Address Bit Permuting (ABP) see Section 6.1.3. The following rules and limitations are required for ABP to operate properly. * * * * * All banks must be in 4:1 interleave mode. There must be a power of two number of banks populated. All banks within an ABP group (2 banks in 2 bank permuting and 4 banks in 4 bank permuting) must be the same size. All populated rows must be adjacent and start at bank 0. Both cards in a system must be configured to allow equivilent ABP settings (i.e., Card 0 and Card 1 must both be configured according to the above rules for the current setting of the ABP enable.)
6.1.2.3
Card to Card (C2C) Interleaving Rules and limitations Card to Card Interleaving is described in detail in Section 6.1.4. All of the ABP rules defined above apply to C2C interleaving, plus the following rules: * * The memory cards must be identically populated with memory DIMMs of the same size and type. The DBC registers must be programmed in the alternate C2C order as defined in the C2C functional description in Section 6.1.4.
6-4
Intel(R) 450NX PCIset
6.1 Overview
6.1.3
Address Bit Permuting
Address Bit Permuting works by increasing the likelihood that requests spaced closely together in time access different banks of memory which will already be closed and precharged. This is achieved by distributing the addresses, on a cache line size granularity, across either two or four banks of memory. The lowest order address bits which define a cache line are used as the bank selects into the memory array so that all requests to a zero based cache line are directed at bank 0. This is illustrated in Figure 6-4.
Request address accesses bank:
4 Bank Permuting
Bank 0 Bank 1 Bank 2 Bank 3
0h, 80h, 100h, .... 20h, A0h, 120h, ... 40h, C0h, 140h, ... 60h, E0h, 160h, ...
Request address accesses bank:
2 Bank Permuting
Bank 0 Bank 1
0h, 40h, 80h, .... 20h, 60h, A0h, ...
Figure 6-4:
Effect of Address Bit Permuting on Bank Access Order
6.1.4
Card to Card (C2C) Interleaving
The purpose of the C2C feature is to further distribute memory accesses across multiple banks of memory as done with the ABP modes. This mode is supported in addition to the standard ABP modes so that maximum distribution of memory accesses and hence, maximum sustained bandwidth can be acheived. The distribution of accesses to each memory card with C2C enabled is by cache line with all even cache lines sent to Card 0 and all odd cache lines sent to Card 1. The feature can be enabled, if all of the restricions are met, by setting bit 2 of the MIOC CONFIG register. With C2C enabled the DRAM Bank Configuration Registers become mapped to the physical memory differently than with C2C disabled (default mode). Figure 6-5 shows both the C2C disabled and enabled modes mapping of DRAM Bank Configuration Registers to physical bank location. With C2C enabled and 2 bank ABP enabled Banks 0, 1, 2 and 3 must all be the same size and type and Banks 4, 5, 6 and 7 (if present) must be the same size and type. With C2C enabled and 4 bank ABP enabled Banks 0 through 7 must all be the same size and type.
Intel(R) 450NX PCIset
6-5
6. Memory Subsystem
With C2C enabled and no ABP enabled each pair of consecutive banks must be of the same size and type. For example Banks 0 and 1 must be the same size and type and Banks 2 and 3 must be the same size and type but need not match Banks 0 and 1.
C2C Disabled Bank Register Ordering
Bank 0 Bank 1 Bank 2 Bank 3 Memory Card 0 Bank 8 Bank 9 Bank 10 Bank 11 Memory Card 1
C2C Enabled Bank Register Ordering
Bank 0 Bank 2 Bank 4 Bank 6 Bank 1 Bank 3 Bank 5 Bank 7
Memory Card 0
Memory Card 1
Figure 6-5:
DRAM Bank Configuration Register Programming with C2C Disabled and Enabled
6.1.5
Memory Initialization
The MIOC provides an MRESET# output, which is asserted on power-good reset, system hard reset, and a BINIT reset. The MRESET# signal is sent to all RCGs and MUXs in the memory subsystem. When asserted, each RCG and MUX clears their transaction queues, data buffers and transaction state. Any transactions that may have been in-progress or pending in the memory subsystem are lost. Note that this may corrupt the contents of the DRAMs, and could leave the DRAMs themselves in an intermediate state, unable to accept a new transaction. Following MRESET# deassertion, the MIOC will re-initialize the memory subsystem by issuing eight CAS#-before-RAS# refreshes per bank (this does not affect the data held in the memory).
6-6
Intel(R) 450NX PCIset
Transaction Summary
7
This chapter describes the transactions supported by the Intel(R) 450NX PCIset.
7.1
7.1.1
Host To/From Memory Transactions
Reads and Writes
The Read transactions supported by the Intel 450NX PCIset are: Partial Reads, Part-line Reads, Cache Line Reads, Memory Read and Invalidate (length > 0), Memory Read and Invalidate (length = 0), Memory Read (length = 0). The Write transactions supported by the Intel 450NX PCIset are: Partial Writes, Part-line Writes, Cache Line Writes.
7.1.2
Cache Coherency Cycles
The MIOC implements an implicit writeback response during system bus read and write transactions when a system bus agent asserts HITM# during the snoop phase. In the read case the MIOC snarfs the writeback data and updates the DRAM. The write case has two data transfers: the requesting agent's data followed by the snooping agent's writeback data.
7.1.3
Interrupt Acknowledge Cycles
A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an 8259-compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial read transaction, except that the address bus does not contain a valid address. The interrupt acknowledge request issued by the processor is deferred by the MIOC and forwarded to PXB #0, which performs a PCI Interrupt Acknowledge cycle on PCI bus #0A (the compatibility PCI bus).
7.1.4
Locked Cycles
The system bus specification provides a means of performing a bus lock. Any Host-PCI locked transaction will initiate a PCI locked sequence. The processor implements the bus lock
Intel(R) 450NX PCIset
7-1
7. Transaction Summary
mechanism which means that no change of bus ownership can occur from the time the agent has established the locked sequence (i.e., asserts LOCK# signal on the first transaction and data is returned) until it is completed. The DRAM is locked from the PCI perspective until the host locked transaction is completed.
7.1.5
Branch Trace Cycles
An agent issues a Branch Trace Cycle for taken branches if execution tracing is enabled. The address Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carries the linear address of the instruction causing the branch and D[31:0]# carries the target linear address. The MIOC will respond and retire this transaction but will not latch the value on the data lines or provide any additional support for this type of cycle.
7.1.6
Special Cycles
Special cycles are used to indicate to the system some internal processor conditions. The first address phase Aa[35:3]# is undefined and can be driven to any value. The second address phase, Ab[15:8]# defines the type of Special Cycle issued by the processor. Table 7-1 below specifies the cycle type and definition as well as the action taken by the MIOC when the corresponding cycles are identified. Table 7-1: MIOC Actions on Special Cycles Ab[15:8] 0000 0000 0000 0001 Cycle Type NOP Shutdown Action Taken This transaction has no side-effects. This cycle is claimed by the MIOC. No corresponding cycle is delivered to the PCI bus. The MIOC asserts INIT# back to the agent for a minimum of 4 clocks. The MIOC claims this cycle and retires it. This cycle is claimed by the MIOC, forwarded to the compatability PCI bus as a Special Halt Cycle, and retired on the system bus after it is terminated on the PCI bus via a master abort mechanism. The MIOC claims this cycle and retires it. The MIOC claims this cycle and retires it. This cycle is claimed by the MIOC and propagated to the PCI bus as a Special Stop Grant Cycle. It is completed on the system bus after it is terminated on the PCI bus via a master abort mechanism. The MIOC's SMIACT# signal will be asserted upon detecting an SMI Acknowledge cycle with SMMEM# asserted, and will remain asserted until detecting a subsequent SMI Acknowledge cycle with SMMEM# deasserted.
0000 0010 0000 0011
Flush Halt
0000 0100 0000 0101 0000 0110
Sync Flush Acknowledge Stop Clock Acknowledge
0000 0111
SMI Acknowledge
all others
Reserved
7-2
Intel(R) 450NX PCIset
7.1 Host To/From Memory Transactions
7.1.7
System Management Mode Accesses
The Intel 450NX PCIset uses an SMRAM configuration register to enable, define and control access to the SMM RAM space. The SMM RAM space defaults to location A000h, with a size of 64 KB, but may be relocated and grown in increments of 64 KB. A master enable (SMRAME) and three access-control enables (Open, Closed, Locked) determine how accesses to the space are to be serviced. Table 7-2 summarizes how accesses to the SMM RAM space are serviced. Table 7-2: SMRAM Space Cycles SMRAME C_CODE D_OPEN SMMEM C_LCK Code Fetch Normal1 PCI 0a DRAM Data Reference Normal1 PCI 0a DRAM
Usage
0 1 1
X 0 0
X 0 0
X X X
X 0 1
SMM RAM space is not supported. Normal SMM usage. Accesses to the SMM RAM space from processors in SMM will access the DRAM. Accesses by processors not in SMM will be diverted to the compatibility PCI bus. A modification of the normal SMM usage, in which only code fetches are accepted from processors in SMM mode. Full access by any agent to SMM RAM space. Typically used by the BIOS to initialize SMM RAM space.
1 1 1
0 0 1
1 1 X
X X 0
0 1 X
PCI 0a DRAM DRAM
PCI 0a PCI 0a DRAM
1. SMRAM functions are disabled. The access is serviced like any other. The address is checked
against the other space and gap definitions to determine its disposition -- to PCI, to memory, or to the system bus for a third party agent to claim.
7.1.8
Third-Party Intervention
The Intel 450NX PCIset supports the same third-party control sideband controls that were defined in Intel 450GX PCIset. These controls allow an external agent on the system bus to affect the way in which the MIOC responds to a system bus request to memory. This external agent is referred to as a "third-party" to the transaction. When a third-party agent intervenes in the normal transaction flow, both the MIOC and the third-party share responsibility for generating the appropriate response; however, the MIOC is always the "owner" of the transaction, and hence must be the responding bus agent. The third-party controls how the MIOC responds by asserting a code on the sideband TPCTL[1:0] signals during the snoop phase. The MIOC samples these signals in the last cycle of the snoop phase. Table 7-3 indicates the actions possible using the TPCTL[1:0] signals.
Intel(R) 450NX PCIset
7-3
7. Transaction Summary
Table 7-3: TPCTL[1:0] Operations TPCTL [1:0] 00 01 10 11 Action Accept. The MIOC accepts the request, and provides the normal response. The third-party agent is not involved in the transaction. Hard Fail. Not supported by the Intel(R) 450NX PCIset. Retry. The MIOC will generate a retry response. The access will be retried by the requesting agent. Defer. The MIOC will issue a defer response, and the third-party agent will complete the transaction at a later time using a deferred reply.
7.2
7.2.1
Outbound Transactions
Supported Outbound Accesses
The PXB translates valid system bus commands into PCI bus requests. For all Host-PCI transactions the PXB is a non-caching agent since the Intel 450NX PCIset does not support cacheability on PCI. However, the PXB must respond appropriately to the system bus commands that are cache oriented.
7.2.2
Outbound Locked Transactions
The Intel 450NX PCIset supports memory-mapped outbound locked operations. I/Omapped outbound locked transactions are not supported. Further, a locked transaction cannot be initiated with a zero-length read. These restrictions are consistent with the transactions supported by the processor.
7.2.3
Outbound Write Combining
The Intel 450NX PCIset provides its own write combining for Host-PCI write transactions. If enabled, and multiple Host-PCI writes target sequential locations in the PCI space, the data is combined and sent to the PCI bus as a single write burst. This holds true for all memory attributes, not just WC. There is no corresponding write-combining for the Host-DRAM path.
7.2.4
Third-Party Intervention on Outbounds
The use of the third-party control signals (TPCTL) is not supported for outbound transactions (Host-PCI). Assertion of the TPCTL signals during an outbound transaction will have
7-4
Intel(R) 450NX PCIset
7.3 Inbound Transactions
indeterminate results. Assertion of DEFER# during an outbound transaction will also have indeterminate results.
7.3
Inbound Transactions
For all inbound transactions, the Intel(R) 450NX MIOC will use an Agent ID of `1001b (9). This is the same agent ID used by the Intel 450GX PCIset, which the Intel 450NX PCIset replaces. Note that memory-mapped accesses across PCI buses (i.e., peer-to-peer transfers) are not supported. Also, inbound I/O transactions are not supported, either to other PCI buses or to the system bus.
7.3.1
Inbound LOCKs
Inbound (PCI-to-system bus) LOCKs are not supported in the Intel 450NX PCIset. Use of inbound locks on the Intel 450NX PCIset may result in unanticipated behavior. The Intel 450NX PCISet is NOT compatible with devices on the compatibility PCI bus which are capable of initiating inbound bus- or resource-locks. Deadlock may occur between outbound locked transactions, south bridge-initiated Secure Sideband Requests (PHOLD#), and LOCK# assertion by the offending device. Devices capable of asserting LOCK# to access memory should not be used on the compatibility PCI bus.
7.3.2
South Bridge Accesses
The PXB's Bus `a' has sideband signals to support the PIIX4E south bridge for ISA expansion. The PXB does not support an EISA bridge.
WSC# Handshake
When the PIIX4E south bridge issues an interrupt for an ISA master, it must first check that any writes posted from ISA to memory have been observed before the interrupt is issued. This action is necessary to guarantee that an ISA write followed by an ISA interrupt is observed in that same order by a processor on the system bus. Whenever the compatibility bus PXB receives a write from the south bridge, it will deassert the WSC# (Write Snoop complete) signal. WSC# will remain de-asserted until the write Completion for that write has returned. When the Completion returns, WSC# is again asserted. While WSC# is de-asserted the PXB must retry any additional writes from the south bridge. The PXB will only support the WSC# Handshake when the internal arbiter is used. When operating in external arbiter mode, the PXB will always hold WSC# asserted. The WSC# mode may be disabled by a bit in the PXB's CONFIG register. If disabled, WSC# stays asserted and inbound writes from the south bridge are accepted.
Intel(R) 450NX PCIset
7-5
7. Transaction Summary
Distributed DMA
Distributed DMA across the PCI bus is not supported by the Intel 450NX PCIset. This function is incompatible with the passive release mechanism portion of the PHOLD#/PHLDA# protocol used to grant PCI bus access to south bridges.
Accesses Prohibited to Third-Party Agent
The Intel 450NX PCIset only supports inbound south bridge accesses to memory. Inbound accesses from a south bridge using the PHOLD#/PHLDA# protocol, directed to a third-party agent on the system bus, are not supported. Such accesses, involving interactions with unknown and unpredictable agents, could violate the rules governing the PHOLD#/PHLDA# protocol, potentially leading to deadlocks.
7.4
Configuration Accesses
The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The Intel(R) 450NX PCIset supports only Mechanism #1. Mechanism #1 defines two I/O-space locations: an address register (CONFIG_ADDRESS) at location 0CF8h, and a data register (CONFIG_DATA) at location 0CFCh. The Intel 450NX PCIset provides a PCI-compatible configuration space for the MIOC, and one for each PCI bus in the PXB. * If the MIOC detects the I/O request is a configuration access to its own configuration space, it will service that request entirely within the MIOC. Reads result in data being returned to the system bus. If the MIOC detects the I/O request is a configuration access to a PXB configuration space, it will forward the request to the appropriate PXB for servicing. The request is not forwarded to a PCI bus. Reads will result in data being returned by the PXB through the MIOC to the system bus. If the MIOC detects the I/O request is a configuration access to a third-party agent on the system bus, it will leave the access unclaimed on the system bus. The third-party agent may claim the access, with reads resulting in data being returned by the third-party agent to the system bus. Otherwise, the access is forwarded on to the PXB to be placed on the PCI bus as a Configuration Read or Configuration Write cycle. Reads will result in data being returned through the PXB and MIOC back to the system bus, just as in normal Outbound Read operations.
*
*
*
7-6
Intel(R) 450NX PCIset
Arbitration, Buffers & Concurrency
8
8.1
PCI Arbitration Scheme
The PCI Specification Rev 2.1 requires that the arbiter implement a fairness algorithm to avoid deadlocks and that it assert only a single GNT# signal on any rising clock. The arbitration algorithm is fundamentally not part of the PCI Specification. The PXB contains an internal PCI arbiter. This arbiter can be disabled either when the PXB operates with I/O bridges which include this function, or when a customized PCI arbiter solution is required. The Internal PCI Arbiter has the following features:
* * * * * * * * *
Support for 6 PCI masters, Host and I/O Bridge 2 Level Round Robin Bus Lock Implementation Bus Parking on last agent using the bus 4-PCI clock grant (FRAME#) time-out Multi Transaction Timer (MTT) mechanism PCI arbitration is independent from the system bus arbitration PIIX4E- compatible protocol (EISA bridges are not supported) PCI Protocol Requirements
8.2
Host Arbitration Scheme
The system bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The processors arbitrate for the system bus as symmetric agents using their own signaling. Symmetric agents implement fair, distributed arbitration using a round-robin algorithm. The MIOC, as an I/O agent, uses a priority agent arbitration protocol to obtain the ownership of the system bus. Priority agents use the BPRI# signal to immediately obtain bus ownership. Besides two classes of arbitration agents (symmetric and priority agents), each bus agent has two mechanisms available that act as arbitration modifiers: the bus lock (LOCK#) and the request stall (BNR#).
Intel(R) 450NX PCIset
8-1
8. Arbitration, Buffers & Concurrency
8.2.1
Third Party Arbitration
The Intel 450NX PCIset requests the system bus with BPRI#. If multiple bridges or a third party agent is on the system bus, an arbitration method is required to establish bus ownership among multiple requesting bridges (which bridge can drive BPRI#). This arbitration is transparent to the Pentium(R) II XeonTM processors or other symmetric bus agents. Only one bridge is allowed to drive BPRI# at a time.
8.3
South Bridge Support
The Intel(R) 450NX PCIset is designed to work with the PIIX4E south bridge which connects the PCI bus to ISA bus and I/O APIC components. Note that the protocols described here apply only when the Intel 450NX PCIset is used in internal arbiter mode -- use of the PIIX4E in external arbiter configurations is not supported. The Intel 450NX PCIset does not guarantee ISA access latencies of < 2.5 usec. ISA devices which require these latencies to be met (GAT mode timing) are not supported.
8.3.1
I/O Bridge Configuration Example.
The basic I/O bridge configuration supported by the Intel 450NX PCIset is shown in Figure 81. The figure shows the sideband signals that connect the PXB to the PIIX4E, I/O APIC components and the external arbiter. Note that PHOLD#/PHLDA# are connected between PXB and the PIIX4E, and WSC# output from PXB is connected to the APICACK2# input of the stand-alone I/O APIC component. If the configuration does not have I/O APIC component, then WSC# pin is left unconnected.
REQ#[0:5] PHLDA# PHOLD#
GNT#[0:5] EXTARB NC
PXB
WSC#
PCI bus
PHOLD# PHLDA#
APICREQ# APICACK#
APICREQ# APICACK#
APICACK2#
PIIX4E
I/O APIC
Figure 8-1:
ISA Bridge with the I/O APIC (Internal Arbiter)
8-2
Intel(R) 450NX PCIset
8.3 South Bridge Support
8.3.2
PHOLD#/PHLDA# Protocol
The PIIX4E uses only two signals to obtain the ownership of the PCI bus. The PIIX4E will assert PHOLD# to indicate that an ISA master is requesting to run a cycle (DREQ active) or an integrated PCI-IDE bus-mastering device is requesting the PCI bus.
DREQ#
DGNT# PHOLD# passive bus release passive bus release
active bus release
PHLDA#
Figure 8-2:
PHOLD#/PHLDA# Protocol Showing Active and Passive Bus Release
8.3.3
WSC# Protocol
The WSC# (Write Snoop Complete) is a status signal output from the Intel 450NX PCIset PXB. The WSC# assertion indicates that all necessary snoops for a previously posted PCI-DRAM write have been completed on the system bus. The WSC# signal is primarily used by the I/O APIC device connected to the ISA bridge. The I/O APIC uses this signal to maintain data coherency and ordering of transactions in the system.
NOTE The WSC# Handshake only applies if the PXB is in internal arbiter mode.
Intel(R) 450NX PCIset
8-3
8. Arbitration, Buffers & Concurrency
PCLK FRAME# C/BE# AD(31:0)# IRDY# DEVSEL# STOP# TRDY# WSC# PHOLDA#
Figure 8-3:
WSC# Signal Functionality
8-4
Intel(R) 450NX PCIset
Data Integrity & Error Handling
9
This chapter describes the data integrity support and general error detection and reporting mechanisms used in the Intel(R) 450NX PCIset.
9.1
DRAM Integrity
Both the system data bus and the Intel(R) 450NX PCIset's memory subsystem use a common Error Correcting Code which provides SEC/DED/NED coverage. The ECC used is capable of correcting single-bit errors and detecting 100% of double-bit errors over one code word.
9.1.1
ECC Generation
When enabled, the DRAM ECC mechanism allows automatic generation of an 8-bit protection code for the 64-bit (Qword) of data during DRAM write operations. Note that when ECC is intended to be enabled, the whole DRAM array must be first initialized by doing writes before the DRAM read operations can be performed. This will establish the correlation between 64-bit data and associated 8-bit ECC code which does not exist after power-on. This function is not provided by hardware.
9.1.2
ECC Checking and Correction
During DRAM read operations, a full Qword of data (8 bytes) is always transferred from the DRAM to the MIOC regardless of the size of the originally requested data. Both 64-bit data and 8-bit ECC code are transferred simultaneously from the DRAM to the MIOC. The ECC checking logic in the MIOC uses the received 72 bit Data + ECC to generate the check syndrome. If a single-bit error is detected the ECC logic corrects the identified incorrect data bit.
9.1.3
ECC Error Reporting
When ECC checking is enabled, single-bit and multiple-bit errors detected by the ECC logic are logged in the MIOC. The first two errors detected on reads-from-memory are logged, as are the first two errors detected on data received from the system bus. For memory errors, the error type (single-bit or multi-bit), syndrome, chunk and effective address are logged. The first two memory errors (single-bit or multi-bit) will be logged in the
Intel(R) 450NX PCIset
9-1
9. Data Integrity & Error Handling
MEL and MEA registers. For bus errors, the error type, syndrome and chunk are logged. The first two system bus errors (single-bit or multi-bit) will be logged in the HEL registers. All ECC error logging registers are sticky through reset, allowing software to determine the source of an error after restoring the system to functioning mode. The logging registers hold their values until explicitly cleared by software.
Error Signaling Mechanism
Single-bit correctable errors are not critical from the point-of-view of presenting the correct value of data to the system. The DRAM (if the cause of error is a DRAM array) will still contain faulty data which will cause the repetition of error detection and recovery for the subsequent accesses to the same location. Multi-bit uncorrectable errors are fatal system errors and will cause the MIOC to assert the BERR# signal if enabled in the ERRCMD register. The uncorrected data is forwarded to its destination. For the first two multi-bit uncorrectable errors, the MIOC will log in the MEA register the row number where the error occurred. This information can be used later to point to a faulty DRAM DIMM. The MEA/MEL registers log only the first two errors. After the first two errors have been logged, the MEA/MEL registers will not be updated. However, normal error detection still continues, the ERR[1:0]# and BERR# signals are still asserted as appropriate, and scrubbing of the memory still continues.
9.1.4
Memory Scrubbing
The Intel 450NX PCIset provides a "scrub-on-error" (demand scrubbing) mechanism, wherein corrected data for single-bit errors will be automatically written back into the memory subsystem by the MIOC. Note that this is not the same as "walk-through" scrubbing, in which every memory location is systematically accessed, checked and corrected on a regular basis. The scrub-on-error mechanism will scrub only those locations accessed during normal operation and thus complements the software controlled "walk-through" scrubbing.
9.1.5
Debug/Diagnostic Support
The MIOC supports in-system testing of ECC functions. An ECC Mask Register (ECCMSK) can be programmed with a masking function. Subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of the memory locations written while masked will return an invalid ECC code. If the mask register is left at 0h (the default), the normal computed ECC is written to memory.
9.2
System Bus Integrity
A variety of system bus error detection features are provided by the MIOC. Particularly, the system data bus is checked for ECC errors on Host-DRAM and Host-PCI writes.
9-2
Intel(R) 450NX PCIset
9.3 PCI Integrity
Additionally, the MIOC request/response signals.
supports
parity
checking
on
the
system
address
and
9.2.1
System Bus Control & Data Integrity
The MIOC detects errors on the system data bus by checking the ECC provided with data and the parity flag provided with control signals. In turn, the MIOC will generate new ECC with data and parity with control signals so that bus errors can be detected by receiving clients. The request control signals ADS# and REQ#[4:0] are covered with the Request Parity signal RP#, which is computed as even parity. This ensures that it is deasserted when all covered signals are deasserted. The address signals A#[35:3] are covered by the Address Parity signal AP#[1:0], which is also configured for even parity. This ensures that each is deasserted when all covered signals are deasserted. AP#[1] covers A#[35:24] and AP#[0] covers A#[23:3]. Response signals RS#[2:0] are protected by RSP#. RSP# is computed as even parity. This ensures that it is deasserted when all covered signals are deasserted.
9.3
PCI Integrity
The PCI bus provides a single even-parity bit (PAR) that covers the AD[31:0] and C/BE#[3:0] lines. The agent that drives the AD[31:0] lines is responsible for driving PAR. Any undefined signals must still be driven to a valid logic level and included in the parity calculation. Parity generation is not optional on the PCI bus; however, parity error detection and reporting is optional. The PXB will always detect an address parity error, even if it is not the selected target. The PXB will detect data parity errors if it is either the master or the target of a transaction, and will optionally report them to the system. Address parity errors are reported using the SERR# signal. Data parity errors are reported using the PERR# signal. The ERRCMD (Error Command) register provides the capability to configure the PXB to propagate PERR# signaled error conditions onto the SERR# signal.
9.4
Expander Bus
Each Expander bus has a parity bit covering all data and control signals for each clock cycle. Parity is generated at the expander bus interface by the sender, and checked at the expander bus interface in the receiver. Detected parity errors are reported at the receiving component -- outbound packets report parity errors in the PXB, while inbound packets report parity errors in the MIOC.
Intel(R) 450NX PCIset
9-3
9. Data Integrity & Error Handling
9-4
Intel(R) 450NX PCIset
System Initialization
10
10.1
10.1.1
Post Reset Initialization
Reset Configuration Using CVDR/CVCR
All system bus devices must sample the following configuration options at reset: * * * * * * * * * Address/request/response parity checking: Enabled or Disabled AERR# detection enable BERR# detection enable BINIT# detection enable FRC mode: Enabled or Disabled Power-on reset vector: 1M or 4G In-Order Queue depth: 1 or 8 APIC cluster ID: 0, 1, 2, or 3 Symmetric agent arbitration ID: 0, 1, 2, 3
The MIOC provides both the Symmetric Arbitration ID parameter and other parameters. (Refer to the CVDR register description.)
10.1.1.1
Configuration Protocol A Pentium(R) II XeonTM processor-based system is initialized and configured in the following manner. 1. The system is powered. The power-supply provides resets for the Intel(R) 450NX PCIset through the PWRGD signal. The MIOC and PXBs assert their resets while the PWRGD signal is not asserted. PCI reset is driven to tristate the PCI buses in order to prevent PCI output buffers from short circuiting when the PCI power rails are not within the specified tolerances. All Intel 450NX PCIset components are initialized, with their internal registers defaulting to the power-on values. The MIOC will drive the appropriate system bus data lines with the initial configuration values that defaulted in the Configuration Values Driven on Reset (CVDR) register. On the rising edge of RESET#, the MIOC will continue driving the appropriate system bus lines with the configuration values. These values are driven at least one clock after the rising edge of RESET#.
2.
3.
4.
Intel(R) 450NX PCIset
10-1
10. System Initialization
5.
All system bus devices will capture the system configuration parameters from the appropriate system bus lines on the rising edge of RESET#. The MIOC captures these values in its Configuration Values Captured on Reset (CVCR) register. (This allows an external device to over-ride the MIOC default parameters.) All system bus devices are now ready for further programming. The MIOC will respond to BIOS code fetches. If a change in the system bus system configuration is desired, the MIOC's CVDR register can be programmed with the desired values. After the CVDR register is programmed, the MIOC must be programmed to do a hard reset, through the Reset Control (RC) register. When the MIOC performs a hard reset, all system bus devices are again reset. This reset repeats steps 2-8, except that the CVDR register is not effected by the reset. This register is only re-initialized by the PWRGD signal.
6.
7.
8.
9.
10.1.1.2
Special Considerations for Third-Party Agents One of the settings available in the CVDR/CVCR registers allows the Bus In-Order Queue Depth to be set to 1, instead of the usual 8. When IOQ Depth=1, there is a case where a ThirdParty Agent can starve the system bus. Therefore, any system containing a TPA must either: * * require that the TPA back-off its BPRI# arbitration requests sufficiently to allow the symmetric agents access to the bus, or not use IOQ depth=1.
10-2
Intel(R) 450NX PCIset
Clocking and Reset
11
This chapter describes the generation, distribution and interaction between the various clocks in an Intel(R) 450NX PCIset-based system, as well as the various reset functionality supported by the Intel 450NX PCIset.
11.1
Clocking
The Pentium(R) II XeonTM processor uses a clock ratio scheme where the system bus clock frequency is multiplied to produce the processor's core frequency. The MIOC supports a system bus frequency optimized for 100 MHz. The Intel(R) 450NX PCIset should be used at a bus frequency which provides the required clock frequency for the PCI interfaces. The external clock generator is responsible for generating the system clock. The Intel 450NX PCIset's core clock is equal to the system bus clock rate. The Intel 450NX PCIset is responsible for driving the signals which the processor uses to determine the core to bus clock ratio. The MIOC receives an output of a clock generator on the HCLKIN pin, as illustrated in Figure 11-1. The MIOC uses the HCLKIN signal to drive the host and memory interfaces and the core. This clock is doubled for the MD bus and the Expander buses. External Low Skew Clock Driver System Bus CLK Y1 Y2 Y3 Yn HCLKIN MIOC Figure 11-1: Host Clock Generation and Distribution
PCI clock distribution is illustrated in Figure 11-2. The PXB provides a PCI bus clock that is generated by dividing the internal host clock frequency by three. The PCI clock is output through the PCLK pin. Externally this PCI clock drives a low skew clock driver which in turn supplies multiple copies of the PCI clock to the PCI bus. One of the outputs of the external clock driver is fed back into the PXB. A PLL in the PXB forces the external PCI clock to phase lock to the internal PCI clock tree.
Intel(R) 450NX PCIset
11-1
11. Clocking and Reset
Pull-up/Pull-down Detect Host CLK/ 3 PCLK
VCC
External Low Skew Clock Driver A Y1 Y2 Y3 Yn
PCLKFB PXB Figure 11-2: PCI Clock Generation and Distribution
11.2
System Reset
Five varieties of reset functions are supported by the Intel(R) 450NX PCIset. - A Power-Good Reset is triggered by an externally generated signal which indicates that the power supplies and clocks are stable. This reset clears all configuration and transaction state in the Intel 450NX PCIset, as well as asserting resets to the processors, PCI buses, and PIIX, if present. - A System Hard Reset is a software-initiated reset that performs nearly the same functions as the power-good reset. The key difference is that the system hard reset does not clear "sticky" error flags in the Intel 450NX PCIset, thus allowing an error handler to determine the cause of a failure that resulted in reset. Also, hard reset may optionally trigger the processor's Built-In Self-Test (BIST). - A Soft Reset is another software-initiated reset which affects only the processors. This reset may also be generated by certain I/O activities. - A BINIT Reset results from a catastrophic transaction error on the system bus. The memory and the MIOC's configuration space are untouched. - A PXB Reset is a software-initiated reset that affects only a single PXB and its dependent PCI buses. This reset may be used in high-availability systems, where it is desirable to allow the processors and one PXB to continue operation in the event of failure of a single PXB.
11.2.1
Intel(R) 450NX PCIset Reset Structure
Figure 11-3 shows the recommended reset structure for an Intel 450NX PCIset-based system including the PIIX4E south bridge. Note that the primary system power-good signal is provided to the MIOC, which then distributes a variety of reset signals to the rest of the system.
11-2
Intel(R) 450NX PCIset
11.2 System Reset
RESET# INIT#
RESET# INIT#
82C42 A20M#, INTR, NMI#, IGNE# frequency select logic
Processor
Processor
BINIT#
BINIT#
... A20M#,IGNE#, INTR,NMI#
System Bus CRESET# Power Good PWRGD MIOC RESET# BINIT# MRESET# PWRGDB RCG X1RST# X0RST# Mux RCG Mux Memory Card #0 Memory Card #1
X1 Bus
X0 Bus
PIIXOK# PXB #1 PCI Bus #1B PCI Bus #1A PXB #0 PCI Bus #0B PCI Bus #0A
PIIXOK#
CPURST PWRGD RSTDRV
PBRST#
PARST#
PBRST#
PARST#
Figure 11-3: Recommended RESET Distribution for Intel(R) 450NX PCIset-Based Systems Including a PIIX4E South Bridge
Power Good
The reference system shown here assumes a single "power good" signal that indicates clean power supplies and clocks to the MIOC and both PXBs. For routing convenience and drive capability, the MIOC provides a buffered version of its PWRGD input (PWRGDB), which should be connected to the PWRGD inputs of each PXB. Refer to the Electrical Characteristics for additional PWRGD requirements.
RESET#
The RESET# signal is directed to the processors. Assertion of this signal puts all processors in a known state, and invalidates their L1 and L2 caches. When this signal is deasserted, the processor begins to execute from address 00_FFFF_FFF0h. The Boot ROM must respond to this address range regardless of where it physically resides in the system.
CRESET#
The CRESET# signal tracks RESET#, but is held asserted two clocks longer than RESET#. It is provided to allow an external frequency selection mux to drive the system-bus-to-core-clock ratio onto pins LINT[1:0], IGNNE#, and A20M# of the system bus during RESET#.
PCIRST (unused)
ISA
PIIX4E
Intel(R) 450NX PCIset
11-3
11. Clocking and Reset
MRESET#
The MRESET# signal is sent to all RCGs and MUXs in the memory subsystem. When asserted, each RCG and MUX clears their transaction state and data buffers. Any transactions that may have been in-progress or pending in the memory subsystem are lost. Upon MRESET# deassertion, the MIOC will re-initialize the memory subsystem by issuing 8 CASbefore-RAS refreshes per bank (this does not affect the data held in the memory).
SYSTEM Bus CLK PWRGD
2ms req'd
1ms
Core & Exp. Clocks Internal Reset# MRESET# MIOC RESET#
2 Hclk 2ms
CRESET#
2ms
BNR# X(0,1)RST#
tristate
Expander
Expander Buses
held in reset
resynch
ready
1ms
Core Clock PCI CLK
relock (1ms)
PXB
PWRGDB
1ms
Internal Reset# P(A,B)RST# = PIIX4E PWROK
1ms req'd
RSTDRV PIIX CPURST = PXB PIIXOK#
1ms 2ms
Figure 11-4: Power-Good Reset
11-4
Intel(R) 450NX PCIset
11.2 System Reset
Soft Reset
A Soft Reset is a reset directed to the processors on the system bus which does not affect the configuration or transaction state of the Intel 450NX PCIset or the dependent PCI buses. To support this function, the system design must externally combine the MIOC's INIT# output with the I/O port 92h and keyboard controller soft reset sources as shown in Figure 11-5.
Vcc KBC RESET# I/O Port 92 Reset MIOC INIT# 74F07 INIT# (to processors)
Figure 11-5:
Soft Reset
PXB Reset
A PXB Reset is a software-initiated reset that affects only a single PXB and its dependent PCI buses. Figure 11-4 illustrates a software-initiated PXB Reset.
Reset Without Disturbing PCI Clocks
PCICLKA and PCICLKB must be re-phased whenever any type of reset is asserted if the Intel 450NX PCIset is to be deterministic relative to that reset. The behavior of these clocks cannot be guaranteed during this re-phasing. A bit in the PXB RC register can be cleared by a configuration write to defeat the PCI clock re-phasing, so that PCICLKA and PCICLKB remain well behaved through resets.
11.2.2
Output States During Reset
The following tables shows the signal states of the Intel 450NX PCIset components during a Power-Good Reset or System Hard Reset. Inputs are denoted by "-".
Intel(R) 450NX PCIset
11-5
11. Clocking and Reset
S/W
CF8/CFC Write to RC to assert System Hard Reset ADS#
CF8/CFC Write to RC to deassert System Hard Reset
2ms 2ms
MIOC Expander
BNR# X(0,1)RST#
67 Hclk
Expander Buses
held in reset
resynch
ready
PCI CLK
relock (1ms)
Internal Reset# P(A,B)RST# = PIIX4E PWROK
PXB
64 Hclk
RSTDRV PIIX CPURST = PXB PIIXOK#
1ms 2ms
Figure 11-6: Software-Initiated PXB Reset
11.2.2.1
MIOC Reset State Host Interface A[35:3]# ADS# AERR# AP[1:0]# BERR# BINIT# BNR# BP[1:0]# BPRI# BREQ[0]# D[63:0]# DBSY# DEFER#
Tristate1 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Asserted2 Tristate Tristate Tristate
DEP[7:0]# DRDY# HIT# HITM# INIT# LOCK# REQ[4:0]# RP# RS[2:0]# RSP# TRDY#
Tristate Tristate Tristate3 Tristate Tristate Tristate Tristate Tristate
11-6
Intel(R) 450NX PCIset
11.2 System Reset
Third-Party Agent Interface IOGNT# IOREQ# Tristate Memory Subsystem / External Interface BANK[2:0]# Deasserted CARD[1:0]# Deasserted CMND[1:0]# Deasserted CSTB# Deasserted DCMPLT(a,b)# Tristate DOFF[1:0]# Deasserted DSEL[1:0]# Deasserted DSTBN[3:0]# Tristate DSTBP[3:0]# Tristate Expander Interface (two per MIOC: 0,1) X(0,1)ADS# Tristate X(0,1)BE[1:0]# Tristate X(0,1)BLK# Deasserted X(0,1)CLK Toggling X(0,1)CLKB Toggling X(0,1)CLKFB X(0,1)D[15:0]# Tristate X(0,1)HRTS# Toggling X(0,1)HSTBN# Toggling Common Support Signals CRES[1:0] Strapped TCK TDI TDO OD Component-Specific Support Signals CRESET# Asserted ERR[1:0]# Tristate HCLKIN Toggling INTREQ# Deasserted
Notes:
1.
TPCTL[1:0]
-
DVALID(a,b)# MA[13:0]# MD[71:0]# MRESET# PHIT(a,b)# ROW# RCMPLT(a,b)# RHIT(a,b)# WDEVT# X(0,1)HSTBP# X(0,1)PAR# X(0,1)RST# X(0,1)RSTB# X(0,1)RSTFB# X(0,1)XRTS# X(0,1)XSTBN# X(0,1)XSTBP#
Deasserted Deasserted Tristate Asserted Deasserted Deasserted Toggling Tristate Asserted Asserted -
TMS TRST# VCCA (3) VREF (6) PWRGD PWRGDB RESET# SMIACT#
Reference Reference -4 De/asserted4 Asserted Deasserted
The Pentium(R) II XeonTM processor allows for configuring a variety of processor and bus variables during the reset sequence. During RESET# assertion, and for one clock past the trailing edge of RESET#, the Intel 450NX PCIset MIOC will drive the contents of its CVDR register onto A[15:3]#. All system bus devices (including the MIOC) are required to sample these address lines using the trailing edge of reset, and modify their internal configuration accordingly. Note the initial value of CVDR may be changed by the boot processor, and the reset process re-engaged. This allows the processors and buses to power-up in a "safe" state, yet allow re-configuration based on specific system constraints. BREQ0# must stay asserted (low) for a minimum of 2 system clocks after the rising edge of RESET#. The MIOC then releases (tristates) the BREQ0# signal. INIT# is not asserted during power-up. It may be optionally asserted during system hard reset through the RC register to cause the processors to initiate BIST. The PWRGDB output is asserted if the PWRGD input is asserted (i.e., a power-good reset). For a system hard reset, the PWRGDB output is deasserted.
2. 3. 4.
Intel(R) 450NX PCIset
11-7
11. Clocking and Reset
11.2.2.2
PXB Reset State PCI Bus Interface (2 per PXB: A,B) Tristate P(A,B)AD[31:0] P(A,B)PAR Tristate P(A,B)C/BE[3:0]# P(A,B)PERR# P(A,B)CLKFB P(A,B)REQ[5:0]# Toggling P(A,B)CLK P(A,B)RST# Tristate P(A,B)DEVSEL# P(A,B)SERR# Tristate P(A,B)FRAME# P(A,B)STOP# Tristate P(A,B)GNT[5:0]# P(A,B)TRDY# Tristate P(A,B)IRDY# P(A,B)XARB# Tristate P(A,B)LOCK# PCI Bus Interface / Non-Duplicated (one set per PXB) Tristate ACK64# PHLDA# Strapped MODE64# REQ64# PHOLD# WSC# Expander Interface (one per PXB) Tristate XADS# XHSTBP# Tristate XBE[1:0]# XIB XBLK# XPAR# XCLK XRST# Toggling Tristate XD[15:0]# XXRTS# XHRTS# XXSTBN# XHSTBN# XXSTBP# Common Support Signals Strapped CRES[1:0] TMS TCK TRST# TDI VCCA (3) OD TDO VREF (2) Component-Specific Support Signals Deasserted PIIXOK# INTRQ(A,B)# Strapped LONGXB# PWRGD Tristate P(A,B)MON[1:0]#
Note: The P(A,B)REQ[5:0]# signals are inputs to the PXB. During reset, these inputs are ignored. However, these signals become "live" immediately following reset desassertion. All unconnected REQ# inputs should be strapped deasserted. All connected REQ# inputs should have weak pullups.
Tristate Tristate - (see note) Asserted Open Tristate Tristate Strapped
Tristate Asserted Tristate Deasserted Tristate Asserted Deasserted Deasserted Deasserted Reference Reference -
11-8
Intel(R) 450NX PCIset
11.2 System Reset
11.2.2.3
RCG Reset State Memory Subsystem / External Interface BANK[2:0]# CARD# CMND[1:0]# CSTB# GRCMPLT# Deasserted MA[13:0]# Memory Subsystem / Internal Interface ADDR(A,B,C,D)[13:0] Deasserted AVWP# Deasserted CAS(A,B,C,D)(a,b,c,d)[1:0]# Deasserted LDSTB# Deasserted Common Support Signals CRES[1:0] TCK TDI TDO Tristate Component-Specific Support Signals BANKID# Strapped DR50H# Strapped
MRESET# PHIT# RCMPLT# RHIT# ROW#
Deasserted Deasserted Deasserted -
LRD# RAS(A,B,C,D)(a,b,c,d)[1:0]# WDME# WE(A,B,C,D)(a,b)# TMS TRST# VCCA VREF (2) DR50T# HCLKIN
Deasserted Deasserted Deasserted Deasserted Reference Reference Strapped Toggling
11.2.2.4
MUX Reset State Memory Subsystem / External Interface DCMPLT# Deasserted DOFF[1:0]# DSEL# DSTBP[1:0]# Tristate DSTBN[1:0]# Tristate Memory Subsystem / Internal Interface AVWP# LDSTB# LRD# Q0D[35:0] Tristate Common Support Signals CRES[1:0] Strapped TCK TDI TDO Tristate Component-Specific Support Signals HCLKIN Toggling
DVALID# GDCMPLT# MD[35:0]# MRESET# WDEVT# Q1D[35:0] Q2D[35:0] Q3D[35:0] WDME# TMS TRST# VCCA VREF (2)
Deasserted Tristate Tristate Tristate Tristate Reference Reference
Intel(R) 450NX PCIset
11-9
11. Clocking and Reset
11-10
Intel(R) 450NX PCIset
Electrical Characteristics
12
12.1
12.1.1
Signal Specifications
Unused Pins
For reliable operation, always connect unused inputs to an appropriate signal level. Unused AGTL+ inputs should be connected to VTT. Unused active low 3.3 V-tolerant inputs should be connected to 3.3 V. Unused active high inputs should be connected to ground (V SS). When tying bidirectional signals to power or ground, a resistor must be used. When tying any signal to power or ground, a resistor will also allow for fully testing the processor and PCIset after board assembly. It is suggested that ~10K resistors be used for pull-ups and ~1K resistors be used as pull-downs.
12.1.2
Signal Groups
In order to simplify the following discussion, signals have been combined into groups of like characteristics (see below). Refer to Chapter 2 for a description of the signals and their functions. Table 12-1: Signal Groups MIOC
Pin Group AGTL+ Input
Signals LOCK#, PHIT(a,b)#, RCMPLT(a,b)#, RHIT(a,b)#, X(0,1)RSTFB#, X(0,1)XRTS#, X(0,1)XSTBN#, X(0,1)XSTBP#, HIT#, HITM# BR[0]#, BANK[2:0]#, BREQ[0]#, CARD[1:0]#, CMND[1:0]#, CSTB#, DOFF[1:0]#, DSEL[1:0]#, DVALID(a,b)#, MA[13:0]#, MRESET#, ROW#, X(0,1)BLK#, X(0,1)HRTS#, X(0,1)HSTBN#, X(0,1)HSTBP#, X(0,1)RST#, X(0,1)RSTB#, WDEVT# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BPRI#, D[63:0]#, DBSY#, DCMPLT(a,b)#, DEFER#, DEP[7:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, MD[71:0]#, REQ[4:0]#, RESET#, RP#, RS[2:0]#, RSP#, TRDY#, X(0,1)ADS#, X(0,1)BE[1:0]#, X(0,1)D[15:0]#, X(0,1)PAR# INIT#, TDO IOGNT#, TPCTL[1:0], PWRGD,
Notes
AGTL+ Output
AGTL+ I/O
CMOS 14 mA 2.5 V Open Drain Output (3.3 V Tolerant) CMOS Input 3.3 V
Intel(R) 450NX PCIset
12-1
12. Electrical Characteristics
Table 12-1: Signal Groups MIOC (Continued) CMOS Input 2.5 V (3.3 V Tolerant) CMOS I/O 14mA 2.5 V Open Drain Output (3.3 V Tolerant) CMOS Output 10mA 3.3 V Analog signals Note:
1. HCLKIN is equivalent to the Processor BCLK
HCLKIN, X(0,1)CLKFB, TMS, TDI, TCK, TRST# BP[1:0]#, ERR[1:0]# CRESET#, INTREQ#, IOREQ#, SMIACT#, PWRGDB, X(0,1)CLK, X(0,1)CLKB CRES[1:0], VCCA[2:0], VREF[5:0]
1
Table 12-2: Signal Groups PXB Pin Group AGTL+ Input AGTL+ Output AGTL+ I/O CMOS Input 3.3 V CMOS Output 10mA, 3.3 V CMOS 14mA 2.5 V Open Drain Output (3.3 V Tolerant) CMOS I/O 14mA, 3.3 V Open Drain Output Analog Signals PCI Signals (Non-Duplicated) PCI Signals Signals XBLK#, XHRTS#, XHSTBN#, XHSTBP#, XRST# XIB, XXRTS#, XXSTBN#, XXSTBP# XADS#, XBE[1:0], XD[15:0]#, XPAR# P(A,B)CLKFB, PIIXOK#, PWRGD P(A,B)CLK TDO P(A,B)MON[1:0]# CRES[1:0], VCCA[2:0], VREF[1:0] ACK64#, MODE64#, PHOLD#, PHLDA#, REQ64#, WSC# INTRQ(A,B)#, P(A,B)AD[31:0], P(A,B)C/BE#[3:0], P(A,B)DEVSEL#, P(A,B)FRAME#, P(A,B)GNT[5:0]#, P(A,B)IRDY#, P(A,B)LOCK#, P(A,B)PAR, P(A,B)PERR#, P(A,B)REQ(5:0)#, P(A,B)RST#, P(A,B)SERR#, P(A,B)STOP#, P(A,B)TRDY#, P(A,B)XARB# Notes
CMOS Input 2.5 V (3.3 V Tolerant) XCLK, TMS, TDI, TCK, TRST#
Table 12-3: Signal Groups MUX Pin Group AGTL+ Input AGTL+ I/O CMOS Input 2.5 V (3.3 V Tolerant) CMOS 14mA, 2.5 V Open Drain Output (3.3 V Tolerant) CMOS I/O 10mA, 3.3 V Analog Signals Signals AVWP#, DOFF[1:0]#, DSEL#, DVALID#, LDSTB#, LRD#, WDEVT#, WDME#, MRESET# DCMPLT#, DSTBP[1:0]#, DSTBN[1:0]#, GDCMPLT#, MD[35:0]# HCLKIN, TMS, TDI, TCK, TRST# TDO Q0D[35:0], Q1D[35:0], Q2D[35:0], Q3D[35:0] CRES[1:0], VCCA, VREF[1:0] Notes
12-2
Intel(R) 450NX PCIset
12.1 Signal Specifications
Table 12-4: Signal Groups RCG Pin Group AGTL+ Input AGTL+ Output AGTL+ I/O CMOS Input 3.3 V CMOS 14mA, 2.5 V Open Drain Output (3.3 V Tolerant) CMOS Output 10mA, 3.3 V Signals BANK[2:0]#, CARD#, CMND[1:0]#, CSTB#, MA[13:0]#, MRESET#, ROW# AVWP#, LDSTB#, LRD#, PHIT#, RCMPLT#, RHIT#, WDME# GRCMPLT# BANKID#, DR50H#, DR50T# TDO ADDR(A,B,C,D)[13:0]#, WE(A,B,C,D)(a,b)#, CAS(A,B,C,D)(a,b,c,d)[1:0]#, RAS(A,B,C,D)(a,b,c,d)[1:0]# CRES[1:0], VCCA, VREF[1:0] Notes
CMOS Input 2.5 V (3.3 V Tolerant) HCLKIN, TMS, TDI, TCK, TRST#
Analog Signals
12.1.3
The Power Good Signal: PWRGD
PWRGD is a 3.3 V-tolerant input to the PCI Bridge and memory controller components. It is expected that this signal will be a clean indication that the clocks and the 3.3 V, VCC_PCI supplies are within their specifications. `Clean' implies that PWRGD will remain low, (capable of sinking leakage current) without glitches, from the time that the power supplies are turned on until they become valid. The signal will then have a single low to high transition to a high (3. V) state with a minimum of 100ns slew rate. Figure 12-1 illustrates the relationship of PWRGD to HCLKIN and system reset signals.
Intel(R) 450NX PCIset
12-3
12. Electrical Characteristics
3.3V
VCC_PCI
HCLKIN
PWRGD <=100ns RESET#
CRESET#
Figure 12-1:
PWRGD Relationship
The PWRGD inputs to the Intel(R) 450NX PCIset and to the Pentium(R) II XeonTM processor(s) should be driven with an "AND" of `Power-Good' signals from the 5 V, 3.3 V and VCCcoreP supplies. The output of this logic should be a 3.3 V level and should have a pull-down resistor at the output to cover the period when this logic is not receiving power.
12-4
Intel(R) 450NX PCIset
12.1 Signal Specifications
12.1.4
LDSTB# Usage
xxQData Latch LDSTB#
D EN
Q
Enabled DFlop DFlop LRD#
D Q EN
Q
To Core
D
HCLKIN
Figure 12-2:
LDSTB# Usage
LDSTB# opens a flow-through latch to enable fine tuning of the read data timing. By adjusting the trace length of the LDSTB# signal it is possible to match the CAS# or RAS# timings (whichever is last) for optimal timing margin on DRAM read cycles.
12.1.5
VCCA Pins
The VCCA inputs provide the analog supply voltage used by the internal PLLs. To ensure PLL stability, a filter circuit must be used from the board VCC. Figure 12-3 shows a recommended circuit. It is important to note that a separate filter for each VCCA pin is necessary to avoid feeding noise from one analog circuit to another.
10 Ohm 1% VCC VCCA
10uF
Figure 12-3:
VCCA filter
Intel(R) 450NX PCIset
12-5
12. Electrical Characteristics
12.2
Maximum Ratings
Table 12-5 contains stress ratings for the Intel(R) 450NX PCIset. Functional operation at the absolute maximum and minimum ratings is neither implied nor guaranteed. The Intel 450NX PCIset should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Intel 450NX PCIset contains protective circuitry to resist damage from static discharge, care should always be taken to avoid high static voltages or electric fields.
Table 12-5: Absolute Maximum Ratings Symbol VCC3 VIN VIN3 VIN5 TSTOR Notes:
1. 2. 3. Parameter applies to the AGTL+ signal groups only. Parameter applies to 3.3 V-tolerant and JTAG signal groups only. Parameter applies to 5 V-tolerant signal groups and PCI signals only. VCC-PCI is the voltage level on the PCI Bus.
Parameter
Min
Max 4.3 Vtt + 0.5 (not to exceed 3.0) VCC3 + 0.9 (not to exceed 4.3) VCC-PCI + 0.5 150
Unit V V V V
o
Notes
3.3 V Supply Voltage with respect to -0.5 VSS AGTL+ Buffer DC Input Voltage with respect to VSS 3.3 V Tolerant DC Input Voltage with respect to VSS -0.5 -0.5
1 2 3
5 V Tolerant DC Input Voltage with -0.5 respect to V SS Storage Temperature -65
C
11nSec Overvoltage Waveform Voltage Source Impedance R = 55 Ohms 3.3V Supply
4 nSec (max) 4 nSec (max)
(m in) + 11V 11V, p-to-p (minimum)
0V
Input Buffer R
62.5nSec (16Mhz)
5.25V V 10.75V, p-to-p (minimum) -5.5V
Undervoltage Waveform Voltage Source Impedance R= 25 Ohms
Figure 12-4: Maximum AC Waveforms for 5 V Signaling (PCI Signals)
12-6
Intel(R) 450NX PCIset
12.3 DC Specifications
11nSec Overvoltage Waveform Voltage Source Impedance R = 29 Ohms 3.3V Supply
4 nSec (max) 4 nSec (max)
(m in) +7.1V 7.1V, p-to-p (minimum)
0V
Input Buffer R
62.5nSec (16Mhz)
+3.6V V 7.1V, p-to-p (minimum) Undervoltage Waveform Voltage Source Impedance R= 28 Ohms -3.5V
Figure 12-5: Maximum AC Waveforms for 3.3 V Signaling (PCI Signals)
12.3
DC Specifications
Table 12-6 through Table 12-10 list the DC specifications associated with the Intel(R) 450NX PCIset. Care should be taken to read any notes associated with each parameter listed. Table 12-6: Intel(R) 450NX PCIset Power Parameters
Symbol VCC3 VCC-PCI (3.3) VCC-PCI (5) ICC-PCI TC Notes:
1. 2. 3. 4. 5.
Parameter Device VCC PCI VCC for 3.3 V PCI Operation PCI VCC for 5.0 V PCI Operation Clamping Diode Leakage Current Operating Case Temperature
Mi n 3.13 3.0 4.5
Typ 3.3 3.3 5.0
Max 3.46 3.6 5.5 2
Unit V V V mA
o
Notes 1 2, 4 2, 4, 5 3
0
85
C
3.3 V +/-5%. The Intel(R) 450NX PCIset PXB will support either a 5 V or 3.3 V PCI Bus. At 33 MHz. From PCI Specification Rev 2.1. Pin List VCC (A-N).
Intel(R) 450NX PCIset
12-7
12. Electrical Characteristics
Table 12-7: Intel(R) 450NX PCIset Power Specifications Symbol PMAX Parameter Max Power Dissipation PXB MIOC MUX RCG ICC3 Max Power Supply Current PXB MIOC MUX RCG ISS Max Power Supply Current PXB MIOC MUX RCG Notes:
1. 2. 3. 4. Frequency = 100 MHz. This specification is a combination of core power (Icc3), and power dissipated in the AGTL+ outputs and I/O. Iss is the maximum supply current consumption when all AGTL+ signals are low. The Icc Specification does not include the AGTL+ output current to GND.
Max 7.8 13.2 3.3 2.5 2.2 3.3 0.87 0.7 3.3 18.1 2.5 0.8
Unit W W W W A A A A A A A A
Notes 1, 2, 5 1, 2, 5 1, 2, 5 1, 5 1, 4 1, 4 1, 4 1 1, 3 1, 3 1, 3 1, 3
Table 12-8 lists the nominal specifications for the AGTL+ termination voltage (VTT) and the AGTL+ reference voltage (VREF). Table 12-8: Intel(R) 450NX PCIset AGTL+ Bus DC Specifications Symbol VTT VREF Notes:
1. 2. 3. +/-9% during maximum di/dt and +/- 3% steady state, as measured at component VTT pins. Where VTT tolerance can range from - 9% to +9%, as noted above. VREF should be created from VTT by a voltage divider of 1% resistors.
Parameter Bus Termination Voltage Input Reference Voltage
Min
Typ 1.5
Max
Uni t V
Notes 1 2, 3
2/3 VTT -2% 2/3 VTT
2/3 VTT +2%
V
Some of the signals on the MIOC, PXB, MUX and RCG are in the AGTL+ signal group. These signals are specified to be terminated to 1.5V. The DC specifications for these signals are shown in Table 12-9.
12-8
Intel(R) 450NX PCIset
12.3 DC Specifications
Table 12-9: Intel(R) 450NX PCIset DC Specifications (AGTL+ Signal Groups) Vcc3 = 3.3 V (5%, TCASE = 0 to 85 oC) Symbol VIL VIH VOL VOH IOH IOL ILI IREF ILO CIN CO CI/O Notes:
1. 2. 3. 4. 5. 6. 7.
Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Current Output Low Current Input Leakage Current Reference Voltage Current Output Leakage Current Input Capacitance Output Capacitance I/O Capacitance
Min -0.3 VREF +0.2 1.2 2 38
Max VREF -0.2 2.185 0.6 -20 55 +/- 15 +/- 15 +/- 15 10 10 10
Unit V V V V mA mA uA uA uA pF pF pF
Notes 1 1 2 3
2 4 5 6 7 7 7
VREF worst case. Noise on VREF should be accounted for. Refer to the Pentium(R) Pro Family Developer's Manual for more information on VREF. Parameter measured into a 25 resistor to VTT (1.5 V). A high level is maintained by the external pull-up resistors. AGTL+ is an open drain bus. Refer to the Pentium (R) Pro Family Developer's Manual for information on VTT. (0 < VIN < Vcc3) Total current for all VREF pins. (0 < VOUT < Vcc3) Total of I/O buffer and package parasitics.
Table 12-10: Intel(R) 450NX PCIset DC Specifications (Non AGTL+ Groups) Vcc3 = 3.3 V (5%, TCASE = 0 to 85 oC) Symbol CIN CO CI/O CCLK CTCK IOL-14 IOL-10 VOL Pin Group All All All HCLKIN TCK CMOS 2.5 V OD 14mA Parameter Input Capacitance Output Capacitance I/O Capacitance HCLKIN Input Capacitance TCK Input Capacitance Output Low Current 14.0 10.0 0.45 Min Max 10 10 10 10 8 Unit pF pF pF pF pF mA mA V 2 Notes/Test Conditions 1
CMOS 10mA Output Low Current CMOS 10mA Output Low Voltage
Intel(R) 450NX PCIset
12-9
12. Electrical Characteristics
Table 12-10: Intel(R) 450NX PCIset DC Specifications (Non AGTL+ Groups) (Continued) Vcc3 = 3.3 V (5%, TCASE = 0 to 85 oC) Symbol VOL VOH VOH ILO ILI VIL VIH VIL VIH VIL-PCI VIH-PCI VOL-PCI VOH-PCI IOL-PCI ILI-PCI ILO-PCI Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Except HCLK, TCK VOL = 0.4V (0 < VOUT < Vcc3) (0 < VIN < Vcc3) -100uA for pins with 50K pullups, +100uA for pins with 50K pulldowns. 5 V-tolerant 3.3V I/O buffer. VCC-PCI = PCI Bus Voltage. Determined by 2.5 V connected through a 150 ohm resistor. Measured with 10ma load. Specifications for PCI are from PCI Specification Rev 2.1. 3.3 V-tolerant 2.5 V Input or Output buffer.
Pin Group CMOS 2.5 V OD 14mA CMOS 2.5 V OD 14mA CMOS Input CMOS Input CMOS Input CMOS 2.5 V Input CMOS 2.5 V Input PCI PCI PCI PCI PCI PCI PCI
Parameter Output Low Voltage
Min
Max 0.45
Unit V V
Notes/Test Conditions 11 9 8, 11
CMOS 10mA Output High Voltage Output High Voltage
2.4 -+/-10 +/-10 -0.5 2.0 -0.5 1.7 - 0.5 2.0 0.8 3.6 0.7 3.6 0.8 VCC-PCI +0.5 0.55 2.4 6.0 +/-70 +/-10
CMOS 10mA Output Leakage Current Input Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Input Leakage Current Output Leakage Current
uA uA V V V V V V V V mA uA uA
3 4, 5
11 11 6 6, 7 6 6 6 6 6
12-10
Intel(R) 450NX PCIset
12.4 AC Specifications
12.4
AC Specifications
T3 T5 = CLK Rise Time T6 = CLK Fall Time T3 = CLK High Time T4 = CLK Low Time T1 = CLK Period
T5
1.7V 1.25V 0.7V
T6
HCLKIN
T4
T1
Figure 12-6: CLK Waveform Table 12-11: Intel(R) 450NX PCIset Clock Specifications Vcc3 = 3.3 V (5%, TCASE = 0 to 85 oC) Symbol Parameter Host Interface: Bus Frequency T1 T2 T3 T4 T5 T6 T9 T72 T73 T74 T75 Note:
1.
Min
Max
Unit
Notes
90 10 3 3 0.5 0.5 25 25
100 11.11 +/-100
MHz ns ps ns ns 1 1 1 1 1 1
CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Rise Time CLK Fall Time TCK Frequency TCK Hightime TCK Lowtime TCK rise time TCK fall time
1.5 1.5 16.67
ns ns MHz ns ns
5 5
ns ns
These specifications apply to all clock inputs for all four Intel(R) 450NX PCIset components.
Intel(R) 450NX PCIset
12-11
12. Electrical Characteristics
Table 12-12: Intel(R) 450NX PCIset MIOC AC Specifications Vcc3 = 3. 3V (5%, TCASE = 0 to 85 oC) Symbol T10A Parameter Host Interface: A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BPRI#, D[63:0]#, DBSY#, DEFER#, DEP[7:0]#, DRDY#, REQ[4:0]#, RP#, RS[2:0]#, RSP#, TRDY# BP[1:0] BR0# HIT#, HITM#, LOCK# INIT# Third-Party Agent Interface: T14 T15 T16 IOREQ# IOGNT# TPCTL[1:0] Memory Interface: T11 BANK[2:0]#, CARD[1:0]#, CMND[1:0]#, CSTB#, DOFF[1:0], DSEL[1:0]#, DVALID(a,b)#, MA[13:0]#, ROW#, WDEVT# MRESET# DCMPLT(a,b)# PHIT(a,b)#, RCMPLT(a,b)#, RHIT(a,b)# MD(71:0)#, DSTBP(3:0)#, DSTBN(3:0)# 1.88 1.88 0.63 0.63 -0.15 2.65 ns 8 2.0 2.0 0.5 0.5 0.0 3.5 ns ns ns 3 1.58 0.63 1.0 5.0 1.58 0.63 -0.15 2.65 ns 8 Setup Min Hold Min Delay Min Delay Max Unit Notes
T17 T11 T13A T12
2.0
0.5
1.0 -0.15
5.0 2.65
ns ns ns ns
10 8
9
T11 T10 T13
-0.15 -0.15
2.65 2.65
ns ns ns
7, 8 8
11
11 11
12-12
Intel(R) 450NX PCIset
12.4 AC Specifications
Table 12-12: Intel(R) 450NX PCIset MIOC AC Specifications (Continued) Vcc3 = 3. 3V (5%, TCASE = 0 to 85 oC) Symbol Parameter Expander Interface (two per MIOC:0,1) T21 T23 T11 T39 T25 T70 T71 T70 T21 X(0,1)RST#, X(0,1)RSTB# X(0,1)RSTFB#, X(0,1)XRTS# X(0,1)HRTS# Other CRESET# ERR[1:0]# INTREQ#, SMIACT# PWRGD PWRGDB RESET# Testability Signals: T26 T27 T27 T28 T29 Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD signal. 3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. Min and Max timings are measured with 0pF load. TRST# requires a pulse width of 40 ns. This output is asynchronous. This input is asynchronous. Asynchronous assertion with synchronous deassertion. Min and Max timings are measured with 0pf and 25 Ohms to Vtt. Min and Max timings are measured with 0pf and 150 Ohms to 2.5 V. Min and Max timings are measured with 0pf and 230 Ohm to 3.3 V. See Table 12-16 for source synchronous timings. Minimum pulse width 1.0ms. PWRGDB is the buffered output of PWRGD, and has no relation to HCLKIN.
Setup Min
Hold Min
Delay Min
Delay Max
Unit
Notes
-0.1 1.88 0.63 -0.15 1.0 2.0 0.5 1.0 0.0 4.0 1.0 0.0 -0.1
3.25
ns ns
7, 8
2.65 4.1 5.0 3.5
ns ns ns ns ns
8 3 10 3 1, 6 3, 5, 13 7, 8, 12
3.5 3.25
ns ns
TRST# TMS TDI TDO TDO on/off delay 5.0 5.0 14.0 14.0 1.0 10.0 25.0
ns ns ns ns ns
4, 6 2 2 2, 3 2, 3
Intel(R) 450NX PCIset
12-13
12. Electrical Characteristics
Table 12-13: Intel(R) 450NX PCIset PXB AC Specifications Vcc3 = 3.3 V (5%, TCASE = 0 to 85 oC) Symbol Parameter PCI Interface T30 P(A,B)AD[31:0], P(A,B)C/BE[3:0]#, P(A,B)TRDY#, P(A,B)STOP#, P(A,B)LOCK#, P(A,B)DEVSEL#, P(A,B)PAR, P(A,B)IRDY#, P(A,B)FRAME#, P(A,B)PERR#, P(A,B)XARB# P(A,B)REQ[5:0]# P(A,B)GNT[5:0]# INTRQ(A,B)#, P(A,B)RST#, P(A,B)SERR#, ACK64# PHOLD# PHLDA# REQ64# WSC# Expander Interface (one per PXB) T40 T11 T13 T47 T46 XRST# XXRTS# XHRTS# OTHER P(A,B)MON[1:0]# PIIXOK# Testability Signals: T26 T27 T27 T28 T29 TRST# TMS TDI TDO TDO on/off delay 5.0 5.0 14.0 14.0 1.0 10.0 25.0 ns ns ns ns ns 5, 7 2 2 2, 4 2, 4 4.0 7.0 0.5 0.0 1.0 6.0 ns ns 4 1 1.88 0.63 2.8 0.0 -0.15 2.65 ns ns ns 6 8 7.0 0.0 7.0 7.0 0.0 0.0 2.0 2.0 2.0 12.0 11.0 12.0 7.0 0.0 2.0 11.0 ns 1, 3 Setup Min Hold Min Delay Min Delay Max Unit Notes
T31 T32 T34
12.0
0.0 2.0 2.0 12.0 11.0
ns ns ns
1, 3 1, 3 1, 3
T33 T35 T36 T37 T38
2.0
11.0
ns ns ns ns ns
1, 3 1 1, 3 1, 3 1, 3
12-14
Intel(R) 450NX PCIset
12.4 AC Specifications
Notes:
1. 2. 3. 4. 5. 6. 7. 5 V-tolerant. 3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. Min timings are measured with 0pF load, Max timings are measured with 50pF load. Min and Max timings are measured with 0pF load. TRST# requires a pulse width of 40 ns. This signal has an asynchronous assertion and a synchronous deassertion. This input is asynchronous.
PCI Bus Signal Waveforms: All PCI Bus signals are referenced to the PCLK Rising edge. For more information on the PCI Bus signals and waveforms, please refer to the PCI Specification. Table 12-14: Intel(R) 450NX PCIset RCG AC Specifications Vcc3 = 3.3 V (5%, TCASE = 0 to 85 oC) Symbol Parameter Memory Subsystem/External Interface T50 BANK[2:0]#, CARD#, CMND[1:0]#, CSTB#, MA[13:0]#, ROW# GRCMPLT# PHIT#, RCMPLT#, RHIT# Memory Subsystem/Internal Interface T52 T53 T54 T53 T53 T50 T26 T27 T27 T28 T29 Notes:
1. 2. 3. 4. 5. 6. 7. The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD signal. 3.3- tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. Min and Max timings are measured with 0pF load. TRST# requires a pulse width of 40 ns. Max delay timing requirement from MIOC to RCGs and MUXs is two clock cycles. Asynchronous assertion and synchronous deassertion. Min and Max timings are measured with 0pF and 25 to Vtt (1.5 V). This input is asynchronous.
Setup Min
Hold Min
Delay Min
Delay Max
Unit
Notes
2.80
0.0
ns
T51 T52
2.80
0.0
-0.15 -0.15
2.65 2.65
ns ns
6 6
AVWP#, LRD#, WDME#, LDSTB# CAS(A,B,C,D)(a,b,c,d)[1:0]# ADDR(A,B,C,D)[13:0]# RAS(A,B,C,D)(a,b,c,d)[1:0]# WE(A,B,C,D)(a,b)# Other MRESET# TRST# TMS TDI TDO TDO on/off delay 5.0 5.0 14.0 14.0 2.8 0.0
-0.15 0.0 1.0 0.0 0.0
2.65 3.5 5.5 3.5 3.5
ns ns ns ns ns ns ns ns ns
6 3 3 3 3 5 4, 7 2 2 2, 3 2, 3
1.0
10.0 25.0
ns ns
Intel(R) 450NX PCIset
12-15
12. Electrical Characteristics
Table 12-15: Intel(R) 450NX PCIset MUX AC Specifications Vcc3 = 3.3 V (5%, TCASE = 0 to 85oC) Symbol Parameter Memory Subsystem/ External Interface T60 T61 T60 T67 DCMPLT# DOFF[1:0]#, DSEL#, DVALID#, WDEVT# GDCMPLT# LDSTB# Memory Subsystem/ Internal Interface T62 T62 T68 AVWP#, WDME# LRD# Q0D[35:0], Q1D[35:0], Q2D[35:0], Q3D[35:0] Other T69 T26 T27 T28 T29 Notes:
1. 2. 3. 4. 5. 6. 7. 8. 3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. Min and Max timings are measured with 0pF load. TRST# requires a pulse width of 40 ns. Input timings are referenced from LDSTB# rising edge. Output timings are referenced from HCLKIN. Max delay timing requirement from MIOC to RCGs and MUXs is two clock cycles. Asynchronous assertion and synchronous deassertion. Min and Max timings are measured with 0pF and 25 to Vtt (1.5 V). This input is asynchronous. DOFF[1:0]#, DSEL#, WDEVT# max delay timing requirement from MIOC to MUX is two clock cycles.
Setup Min
Hold Min
Delay Min
Delay Max
Unit
Notes
2.8 2.8 2.8 3.0
0.0 0.0 0.0 1.0
-0.15
2.65
ns ns
6 8 6
-0.15
2.65
ns ns
3.5 3.5 1.0
0.0 0.0 4.0 0.0 3.5
ns ns ns 2, 4
MRESET# Testability Signals: TRST# TMS, TDI TDO TDO on/off delay
2.8
0.0
ns ns
5 3, 7 1 1, 2 1, 2
5.0
14.0 1.0 10.0 25.0
ns ns ns
12-16
Intel(R) 450NX PCIset
12.4 AC Specifications
HCLKIN T63 min DSTBP# X(0,1)HSTBP# X(0,1)XSTBP# T63 max
T64 min
T64 max
T65 min
T65 max
T66 min
T66 max
DSTBN# X(0,1)HSTBN# X(0,1)XSTBN#
Figure 12-7: Source Synchronous Strobe Timing Table 12-16: 100 MHz Source Synchronous Timing Symbol T63 Parameter DSTBP(3:0)#, X(0,1)HSTBP#, X(0,1)XSTBP# Falling Edge DSTBP(3:0)#, X(0,1)HSTBP#, X(0,1)XSTBP# Rising Edge DSTBN(3:0)#, X(0,1)HSTBN#, X(0,1)XSTBN# Rising Edge DSTBN(3:0)#, X(0,1)HSTBN#, X(0,1)XSTBN#, Falling Edge Delay Min 2.35 Delay Max 5.15 Skew Unit ns Notes 1, 2, 4
T64
7.35
10.15
ns
1, 3, 4
T65
2.35
5.15
ns
1, 2, 4
T66
7.35
10.15
ns
1, 3, 4
Intel(R) 450NX PCIset
12-17
12. Electrical Characteristics
Notes:
1. 2. Relative to HCLKIN Rising edge. Strobe timings are generated from an internal clock which is a multiple of HCLKIN. This enables the strobes to track system timings staying centered within the data window. Numbers given are for 100 MHz operation. Timings for other frequencies can be calculated by Strobe_Min_Time = [-0.15 + (1/Bus_Freq)1/ 4] ns and Strobe_Max_Time = [2.65 + (1/Bus_Freq)1 /4] ns. Strobe timings are generated from an internal clock which is a multiple of HCLKIN. This enables the strobes to track system timings staying centered within the data window. Numbers given are for 100 MHz operation. Timings for other frequencies can be calculated by Strobe_Min_Time = [-0.15 + (1/Bus_Freq)3/4] ns and Strobe_Max_Time = [2.65 + (1/Bus_Freq)3/4] ns. Min and Max timings are measured with 0pF and 25 to Vtt (1.5 V).
3.
4.
Table 12-17: Source Synchronous Signal to Strobe Timings (at source) Symbol T80 Parameter MD(71:0)#, X(0,1)D[15:0]#, X(0,1)ADS#, X(0,1)BE[1:0]#, X(0,1)BLK#, X(0,1)PAR# MD(71:0)#, X(0,1)D[15:0]#, X(0,1)ADS#, X(0,1)BE[1:0]#, X(0,1)BLK#, X(0,1)PAR# Setup Min 2.0 Setup Max 2.75 Hold Min Hold Max Notes 1-5
T81
2.0
2.75
1-5
Notes:
1. 2. 3. 4. MD(71:0)# strobes are single-ended, and the falling edge of the strobe is used to capture data; Expander strobes are differential. Values are guaranteed by design. Setup Max and Hold Max are specified at frequency= 100 MHz. Timings for other frequencies can be calculated as follows: T80 Setup_Max = [(1/Bus_Freq)1/4 + .250] ns, T81 Hold_Max = [(1/Bus_Freq)1/4 + .250 ] ns, where .250ns represents the error margin around strobe placement. Data delay times relative to HCLK for any bus frequency can be calculated as follows... For First Data: Data_Min_Time = [-0.15 ]ns and Data_Max_Time = [2.65 ]ns; For Second Data: Data_Min_Time = [-0.15 + (1/Bus Freq)/2 ]ns and Data_Max_Time = [2.65 + (1/Bus Freq)/2 ]ns.
5.
12-18
Intel(R) 450NX PCIset
12.4 AC Specifications
DSTBx# XHSTBx# XXSTBx#
MD(71:0)# XD(15:0)# XBE[1:0]# XPAR# T80 T81 T81
XADS# XBLK#
Figure 12-8: Source Synchronous Signal to Strobe Timings (at source)
Table 12-18: 100 MHz Source Synchronous Timing (at destination) Symbol T20 Parameter DSTBN(3:0)#, DSTBP(3:0)# X(0,1)XSTBN# X(0,1)XSTBP# MD(71:0)# X(0,1)D[15:0]#, X(0,1)ADS#, X(0,1)BE[1:0]#, X(0,1)BLK#, X(0,1)D[15:0]#, X(0,1)PAR# Setup Min 7.0 Hold Min Unit ns Notes 1,4
T24 T22
1.5 1.75
1.5 1.0
ns ns
2 3
Notes:
1. 2. 3. 4. Setup in relation to "capture" HCLKIN. With respect to the DSTBs. With respect to the HSTBs. Applies to Expander bus source synchronous signals. For synchronous signals (RTS#) the maximum clock skew between MIOC and PXB plus the flight time must not exceed 4.97nS.
Intel(R) 450NX PCIset
12-19
12. Electrical Characteristics
1P Launched Here
1P Sampled Here
1P Capture Range T20
HCLK
Data
1P
1N
2P
2N
3P
3N
ODD
EVEN
ODD
STRB
Figure 12-9: Source Synchronous Data Transfer
12.5
Source Synchronous Data Transfers
A Source Synchronous packet has a two clock period delivery time, and is divided into positive and negative phases of even and odd cycles. During this two clock window, packets are launched synchronously and sampled synchronously. Signals launched with a positive phase "even" clock are sampled on a positive phase of next "even" clock. Between launch and sample, signals are captured with source synchronous strobes.
HCLKIN
1.25V
Ts
Th
V
VALID
Ts =Setup Time Th = Hold Time
V =1.0V for AGTL+ 1.5V for 3.3V-tolerant CMOS 1.25V for 2.5V CMOS
Figure 12-10: Setup and Hold Timings
12-20
Intel(R) 450NX PCIset
12.6 I/O Signal Simulations: Ensuring I/O Timings
HCLKIN T x MAX T x MIN
V
Valid
Tx = Valid Delay
Figure 12-11: Valid Delay Timing
12.6
I/O Signal Simulations: Ensuring I/O Timings
It is highly recommended that system designers run extensive simulations on their Pentium(R) II XeonTM processor/Intel(R) 450NX PCIset-based designs. These simulations should include the memory subsystem design as well. Please refer to the Pentium(R) Pro Family Developer's Manual for more information.
12.7
Signal Quality Specifications
Signals driven by any component on the Pentium(R) II XeonTM processor bus must meet signal quality specifications to guarantee that the components read data properly, and to ensure that incoming signals do not affect the long term reliability of the components. There are three signal quality parameters defined: Overshoot/Undershoot, Ringback, and Settling Limit, which are discussed in the next sections.
12.7.1
Intel(R) 450NX PCIset Ringback Specification
This section discusses the ringback specification for the parameters in the AGTL+ signal groups on the Intel(R) 450NX PCIset. Case A requires less time than Case B from the VREF crossing until the ringback into the "overdrive" region. The longer time from VREF crossing until the ringback into the "overdrive" region required in Case B allows the ringback to be closer to VREF for a defined period.
Intel(R) 450NX PCIset
12-21
12. Electrical Characteristics
Table 12-19: Intel(R) 450NX PCIset AGTL+ Signal Groups Ringback Tolerance: Case A Parameter
Overshoot Minimum Time at High or Low Amplitude of Ringback Duration of Squarewave Ringback Final Settling Voltage
Min 100 2.25 -100 N/A 100
Unit mV ns mV ns mV
Figure 12 & 13 12 & 13 12 & 13 12 & 13 12 & 13
Notes 1 1 1 1 1
Note:
1.
Specified for an edge rate of 0.8-1.3 V/ns. See the Pentium(R) Pro Family Developer's Manual for the definition of these terms. See Figure 12-12 and Figure 12-13 for the generic waveforms. All values are determined by design/characterization.
Table 12-20: Intel(R) 450NX PCIset AGTL+ Signal Groups Ringback Tolerance: Case B Parameter
Overshoot Minimum Time at High or Low Minimum Time at Low Amplitude of Ringback Duration of Squarewave Ringback Final Settling Voltage
Min 100 2.7 3.7 -0 2 100
Unit mV ns ns mV ns mV
Figure 12 & 13 12 13 12 & 13 12 & 13 12 & 13
Notes 1 1 1 1 1 1
Note:
1.
Specified for an edge rate of 0.8-1.3 V/ns. See the Pentium(R) Pro Family Developer's Manual for the definition of these terms. See the figures below for the generic waveforms. All values are determined by design/characterization.
12-22
Intel(R) 450NX PCIset
12.7 Signal Quality Specifications
1.25V Clk Ref. 10ps rise/fall edges
V REF + 0 . 2
V
REF
V REF -0.2
Clock
Vstart
Tsu +0.05ns
TIME
Figure 12-12: Standard Input Lo-to-Hi Waveform for Characterizing Receiver Ringback Tolerance
Vstart
Tsu +0.05ns
1.25V Clk Ref.
V REF + 0 . 2
V REF
V REF -0.2
10ps rise/fall edges Clock
TIME
Figure 12-13: Standard Input Hi-to-Lo Waveform for Characterizing Receiver Ringback Tolerance
Intel(R) 450NX PCIset
12-23
12. Electrical Characteristics
12.7.2
Intel(R) 450NX PCIset Undershoot Specification
The undershoot specification for the Intel 450NX PCIset components (and Pentium II Xeon processor) is as follows: The Pentium II Xeon processor bus signals AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM# (only) are capable of sinking an 85mA current pulse at a 2.4% average time duty cycle. This is equivalent to -1.7V applied to a 20 source in series with the device pin for 5.38 ns at 100 MHz with a utilization of 5%.
This test covers the AC operating conditions only
0.5ns (max) +1.7 V 3.4V, p-to-p (max) Voltage source waveform -1.7 V 7.5 ns (max) Average duty cycle of 2.4%.
Figure 12-14: Undershoot Test Setup
R DUT
V
Undershoot Test Waveform Voltage Source Impedance R = 20 ohms
12.7.3
Skew Requirements
The skew requirement for XpRST# versus XpRSTFB#, and XpCLK versus XpCLKFB is +/125ps. The electrical length (delay) from the XpCLK# signal pin on the MIOC to the clock input of the PXB must match the delay to the XpCLKFB# pin on the MIOC by that amount. The same is true with XpRST# and XpRSTFB#.
12-24
Intel(R) 450NX PCIset
12.8 Intel(R) 450NX PCIset Thermal Specifications
12.8
12.8.1
Intel(R) 450NX PCIset Thermal Specifications
Thermal Solution Performance
The system's thermal solution must adequately control the package temperatures below the maximum and above the minimum specified. The performance of any thermal solution is defined as the thermal resistance between the package and the ambient air around the part (package to ambient). The lower the thermal resistance between the package and the ambient air, the more efficient the thermal solution is. The required package to ambient is dependent upon the maximum allowed package temperature (TPackage), the local ambient temperature (TLA), and the package power (PPackage). Package to ambient = (TPackage - TLA)/PPackage TLA is a function of the system design. Table 12-21 and Table 12-22 provide the resulting thermal solution performance required for an Intel(R) 450NX PCIset at different ambient air temperatures around the parts.
Table 12-21: Example Thermal Solution Performance for MIOC at Package Power of 13.2 Watts Local Ambient Temperature (TLA) 35 C
Package to ambient
40 C 3.41
45 C 3.03
C ( Watt )
3.79
Table 12-22: Example Thermal Solution Performance for PXB at Package Power of 7.8 Watts Local Ambient Temperature (TLA) 35 C
Package to ambient C ( Watt )
40 C 5.76
45 C 5.13
6.41
The package to ambient value is made up of two primary components: the thermal resistance between the package and heatsink ( package to heatsink) and the thermal resistance between the heatsink and the ambient air around the part ( heatsink to air). A critical but controllable factor to decrease the value of package to heatsink is management of the thermal interface between the package and heatsink. The other controllable factor ( heatsink to air) is determined by the design of the heatsink and airflow around the heatsink.
Intel(R) 450NX PCIset
12-25
12. Electrical Characteristics
12.9
12.9.1
Mechanical Specifications
Pin Lists Sorted by Pin Number:
Table 12-23: MIOC Pin List Sorted by Pin
Pin # A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 B01
Signal GND GND GND DBSY# A07# GND A13# VTT A20# GND GND A29# A34# GND D01# GND CRES1 D12# GND D19# D22# GND GND D32# VTT D38# GND D46# D49# VCC VCC VCC GND I
I/O
Driver Type Power Power Power
Driver Strength
Internal Pullup/Pulldown
I/O I/O I/O I/O
AGTL+ AGTL+ Power AGTL+ Power AGTL+ Power Power
55ma 55ma 55ma 55ma
I/O I/O I/O
AGTL+ AGTL+ Power AGTL+ Power Analog AGTL+ Power AGTL+ AGTL+ Power Power
55ma
55ma
I/O I/O I/O
55ma 55ma 55ma
I/O I/O I/O I/O
AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power Power Power Power
55ma 55ma 55ma 55ma
12-26
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 C01 C02 C03 C04 C05 C06 C07 Signal GND RS0# A03# GND A10# A14# VTT A21# A24# A27# A30# A35# DRDY# D02# D06# D09# D13# D17# D20# D23# D27# D29# D33# VTT D39# D43# GND D50# D54# VCC VCC GND BNR# RS1# A04# A08# A11# A15# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type Power AGTL+ AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ Power Power Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-27
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 Signal A18# A22# VCC CRES0 A31# VCC VCC D03# VTT VTT D14# VCC VCC D24# VCC N/C D34# D36# D40# D44# D47# D51# D55# D57# VCC BPRI# TRDY# VTT A05# VTT A12# A16# GND A23# A25# A28# A32# BERR# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma I/O I/O I/O I I/O I/O I/O I/O Driver Type AGTL+ AGTL+ Power Analog AGTL+ Power Power AGTL+ Power Power AGTL+ Power Power AGTL+ Power 55ma 55ma 55ma 55ma Driver Strength 55ma 55ma Internal Pullup/Pulldown
12-28
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 Signal D00# D04# D07# D10# D15# D18# D21# D25# D28# D30# D35# GND D41# D45# VTT D52# VTT D58# D60# REQ0# RSP# RS2# A06# A09# VCC A17# A19# GND A26# VTT A33# GND GND D05# D08# D11# D16# GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ Power AGTL+ Power AGTL+ Power Power AGTL+ AGTL+ AGTL+ AGTL+ Power 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-29
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 F01 F02 F03 F04 F05 F28 F29 F30 F31 F32 G01 G02 G03 G04 G05 G28 G29 G30 G31 G32 H01 H02 H03 H04 H05 Signal GND D26# VTT D31# GND D37# D42# VCC D48# D53# D56# D59# D61# GND REQ4# LOCK# REQ1# VCC VCC D62# D63# DEP7# GND GND HIT# VTT REQ2# DEFER# DEP6# DEP5# VTT DEP4# DEP3# AP0# HITM# VTT REQ3# GND I/O I/O I/O I/O I I/O I/O I/O I/O I I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type Power AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ Power Power AGTL+ AGTL+ AGTL+ Power Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ Power 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength Internal Pullup/Pulldown
12-30
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # H28 H29 H30 H31 H32 J01 J02 J03 J04 J05 J28 J29 J30 J31 J32 K01 K02 K03 K04 K05 K28 K29 K30 K31 K32 L01 L02 L03 L04 L05 L28 L29 L30 L31 L32 M01 M02 M03 Signal GND CRESET# DEP2# DEP1# DEP0# AP1# BR0# ADS# RP# GND X0CLKFB BINIT# BP0# BP1# GND ERR0# ERR1# VCC VREF AERR# VCC N/C VCCA0 VCCA1 VCCA2 GND TRST# TCK INTREQ# TMS X0CLK X0CLKB VCC PWRGD GND TPCTL0 VCC TDO O I I I I O I O O Power Power Power Power LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL Power OD 14ma 10ma 10ma 10ma I I/O I/O I/O I I/O I/O I/O O I/O I/O I/O I/O O I/O I/O I/O Driver Type Power LVTTL AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power LVTTL AGTL+ OD OD Power OD OD Power Analog AGTL+ Power 55ma 14ma 14ma 55ma 14ma 14ma 10ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-31
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # M04 M05 M28 M29 M30 M31 M32 N01 N02 N03 N04 N05 N28 N29 N30 N31 N32 P01 P02 P03 P04 P05 P28 P29 P30 P31 P32 R01 R02 R03 R04 R05 R28 R29 R30 R31 R32 T01 Signal TDI GND GND RESET# X1CLK X1CLKB X0RSTFB# VCC TPCTL1 VTT IOREQ# IOGNT# X1CLKFB INIT# X0RSTB# VREF VCC VCC MD00# MD01# MD02# VCC PWRGDB X0RST# X0BE1# X0BE0# VCC GND MD03# MD04# VCC VCC HCLKIN GND X0ADS# X0PAR# X0BLK# MD05# I/O I/O O I/O I I/O I/O O O I/O I/O I/O I/O I/O O I I OD O I I I/O O O I I I/O Driver Type LVTTL Power Power AGTL+ LVTTL LVTTL AGTL+ Power LVTTL Power LVTTL LVTTL LVTTL 2.5V AGTL+ Analog Power Power AGTL+ AGTL+ AGTL+ Power LVTTL AGTL+ AGTL+ AGTL+ Power Power AGTL+ AGTL+ Power Power 2.5V Power AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 10ma 55ma 55ma 55ma 55ma 55ma 55ma 14ma 55ma 10ma 55ma 10ma 10ma Driver Strength Internal Pullup/Pulldown
12-32
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # T02 T03 T04 T05 T28 T29 T30 T31 T32 U01 U02 U03 U04 U05 U28 U29 U30 U31 U32 V01 V02 V03 V04 V05 V28 V29 V30 V31 V32 W01 W02 W03 W04 W05 W28 W29 W30 W31 Signal MD06# MD07# MD08# VCC GND X0D03# X0D02# X0D01# X0D00# DSTBP0# DSTBN0# MD09# GND GND N/C X0D04# VREF X0D05# GND VCC MD10# MD11# GND GND VCC VCC X0XSTBN# X0XSTBP# GND MD12# MD13# MD14# MD15# GND VCC X0XRTS# X0HRTS# X0HSTBN# I O O I/O I/O I/O I/O I I I/O I/O I/O I I/O AGTL+ Analog AGTL+ Power Power AGTL+ AGTL+ Power Power Power Power AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power Power AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ Power Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power Power 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength 55ma 55ma 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-33
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # W32 Y01 Y02 Y03 Y04 Y05 Y28 Y29 Y30 Y31 Y32 AA01 AA02 AA03 AA04 AA05 AA28 AA29 AA30 AA31 AA32 AB01 AB02 AB03 AB04 AB05 AB28 AB29 AB30 AB31 AB32 AC01 AC02 AC03 AC04 AC05 AC28 AC29 Signal X0HSTBP# VCC MD16# VTT MD17# MD18# GND X0D07# VTT X0D06# VCC MD19# MD20# MD21# MD22# GND GND X0D11# X0D10# X0D09# X0D08# GND MD23# VCC MD24# MD25# X0D14# X0D13# VCC X0D12# GND GND MD26# VREF DSTBP1# GND GND X1RST# O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Driver Type AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power AGTL+ Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ Power Power AGTL+ Analog AGTL+ Power Power AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength 55ma Internal Pullup/Pulldown
12-34
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # AC30 AC31 AC32 AD01 AD02 AD03 AD04 AD05 AD28 AD29 AD30 AD31 AD32 AE01 AE02 AE03 AE04 AE05 AE28 AE29 AE30 AE31 AE32 AF01 AF02 AF03 AF04 AF05 AF28 AF29 AF30 AF31 AF32 AG01 AG02 AG03 AG04 AG05 Signal VCC X0D15# VCC DSTBN1# MD27# MD28# MD29# GND GND X1BE1# X1BE0# X1RSTB# X1ADS# GND MD30# VTT MD31# MD32# X1BLK# X1D1# VTT X1D00# GND GND MD33# VTT MD34# MD35# VCC X1D03# VTT X1D02# GND MD36# MD37# MD38# MD39# VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O Driver Type Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ Power Power AGTL+ Power AGTL+ AGTL+ Power AGTL+ Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-35
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # AG28 AG29 AG30 AG31 AG32 AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AJ01 Signal VCC VREF X1D05# X1D04# X1RSTFB# MD40# MD41# MD42# MD43# MD44# VCC MD57# MD62# DSTBN3# VCC VCC DOFF0# GND GND DCMPLTB# ROW# VCC BANK1# GND GND MA07# VTT MA12# GND GND X1D14# VCC X1HSTBN# X1HSTBP# X1XSTBN# X1XSTBP# GND DSTBP2# I/O O O I I I/O O O O I/O O O I/O I/O I/O I I/O I/O I I/O I/O I/O I/O I/O I/O Driver Type Power Analog AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ Power Power AGTL+ Power Power AGTL+ AGTL+ Power AGTL+ Power Power AGTL+ Power AGTL+ Power Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength Internal Pullup/Pulldown
12-36
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # AJ02 AJ03 AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AK01 AK02 AK03 AK04 AK05 AK06 AK07 Signal DSTBN2# VTT MD45# VTT MD54# MD58# GND MD63# MD67# MD71# CMND1# DSEL0# WDEVT# RCMPLTB# DCMPLTA# BANK0# CARD1# GND MA02# MA06# MA09# MA11# GND GND GND X1D13# VTT X1D06# VTT X1XRTS# X1HRTS# VCC MD46# MD47# MD48# MD49# MD55# MD59# I/O I/O I/O I/O I/O I/O I O I/O I/O O O O O I/O I/O I/O O O O I I/O O O I/O I/O I/O I/O I/O Driver Type AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power Power Power AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-37
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # AK08 AK09 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AL01 AL02 AL03 AL04 AL05 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 Signal DSTBP3# MD64# MD68# VCC VCC PHITA# VCC DVALIDA# VTT VTT VCC VCC VCC MA5# VCC VCC GND GND X1D15# GND X1D10# X1D09# X1D08# X1D07# GND VCC VCC MD50# MD51# GND MD56# MD60# VTT MD65# MD69# CMND0# RHITA# MRESET# I/O I/O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I I/O I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ Power Power AGTL+ Power AGTL+ Power Power Power Power Power AGTL+ Power Power Power Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power Power Power AGTL+ AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength 55ma 55ma 55ma Internal Pullup/Pulldown
12-38
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 AM09 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 Signal DSEL1# VREF DVALIDB# PHITB# CARD0# SMIACT# MA01# MA04# MA08# MA10# VCC VTT VTT GND GND X1D12# X1D11# GND GND VCC VCC VCC MD52# MD53# GND MD61# VTT MD66# MD70# GND CSTB# DOFF1# GND RCMPLTA# GND RHITB# BANK2# GND I O I O O I/O I/O I/O I/O I/O I/O I/O I O I O O O O O O I/O O Driver Type AGTL+ Analog AGTL+ AGTL+ AGTL+ LVTTL AGTL+ AGTL+ AGTL+ AGTL+ Power Power Power Power Power AGTL+ AGTL+ Power Power Power Power Power AGTL+ AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power AGTL+ AGTL+ Power AGTL+ Power AGTL+ AGTL+ Power 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 10ma 55ma 55ma 55ma 55ma Driver Strength 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-39
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued) Pin # AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 Signal MA00# MA03# GND GND MA13# VTT VTT GND GND X1PAR# GND GND GND I/O O I/O O O Driver Type AGTL+ AGTL+ Power Power AGTL+ Power Power Power Power AGTL+ Power Power Power Table 12-24: PXB Pinlist Sorted by Pin PIN# A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Signal N/C N/C VCC VCC VCC VCC VCC VCC VCC VCC N/C VREF N/C VCC XD[10]# VCC XHSTBN# VCC XD[04]# VCC XBLK# VCC I I/O I I/O Power AGTL+ Power AGTL+ Power AGTL+ Power AGTL+ Power 55ma 55ma I Analog Power Power Power Power Power Power Power Power I/O Driver Type Driver Strength Internal Pullup/Pulldown 55ma 55ma Driver Strength 55ma 55ma Internal Pullup/Pulldown
12-40
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 Signal N/C VREF N/C VCC VCCA0 VCC VCC N/C N/C N/C N/C VCC VCC VCC N/C N/C N/C N/C N/C N/C N/C N/C N/C XD[15]# XD[11]# XD[08]# N/C XHRTS# XD[05]# XD[02]# XPAR# XBE[01]# N/C N/C N/C N/C N/C VCC Power I I/O I/O I/O I/O AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma I/O I/O I/O AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma Power Power Power Power Power Power Power I Analog I/O Driver Type Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-41
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# B29 B30 B31 B32 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 D01 D02 Signal VCC VCC VCC N/C N/C N/C N/C N/C N/C GND GND GND N/C GND N/C GND N/C GND XD[12]# GND XHSTBP# GND XXSTBN# GND XADS# GND N/C GND XCLK GND VCCA1 N/C N/C N/C N/C N/C N/C GND Power I Power LVTTL Power Power I/O O I I/O Power AGTL+ Power AGTL+ Power AGTL+ Power AGTL+ Power 55ma 55ma 55ma Power Power Power Power Power I/O Driver Type Power Power Power Driver Strength Internal Pullup/Pulldown
12-42
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 E01 E02 E03 E04 E05 E06 E07 E08 Signal N/C VTT N/C N/C N/C N/C CRES1 N/C N/C N/C N/C N/C XD[13]# XD[09]# XD[06]# XXRTS# N/C XD[03]# XD[00]# XRST# N/C N/C N/C N/C VCC VTT PWRGD N/C GND N/C N/C N/C N/C N/C N/C VTT N/C VTT Power Power Power I Power Power LVTTL I/O I/O I AGTL+ AGTL+ AGTL+ 55ma 55ma I/O I/O I/O O AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma I Analog Power I/O Driver Type Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-43
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 F01 F02 F03 F04 F05 F28 F29 F30 F31 F32 G01 G02 G03 G04 Signal CRES0 VTT N/C VTT XIB VTT XD[14]# VTT XD[07]# VTT XXSTBP# VTT XD[01]# VTT XBE[00]# VTT N/C VTT VCCA2 N/C N/C N/C N/C N/C GND N/C VCC N/C GND GND PIIXOK# N/C N/C N/C N/C N/C N/C N/C I Power Power LVTTL Power Power Power Power I/O I/O O I/O I/O O Power AGTL+ Power AGTL+ Power AGTL+ Power AGTL+ Power AGTL+ Power AGTL+ Power 55ma 55ma 55ma 55ma 55ma 55ma I I/O Driver Type Analog Power Driver Strength Internal Pullup/Pulldown
12-44
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# G05 G28 G29 G30 G31 G32 H01 H02 H03 H04 H05 H28 H29 H30 H31 H32 J01 J02 J03 J04 J05 J28 J29 J30 J31 J32 K01 K02 K03 K04 K05 K28 K29 K30 K31 K32 L01 L02 Signal N/C N/C N/C VCC VCC N/C VCC N/C GND N/C VCC N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C PBCLKFB N/C PACLKFB GND N/C VCC N/C GND GND N/C VCC N/C GND GND GND Power Power Power Power Power Power Power I LVTTL Power I LVTTL Power Power Power Power Power Power I/O Driver Type Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-45
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# L03 L04 L05 L28 L29 L30 L31 L32 M01 M02 M03 M04 M05 M28 M29 M30 M31 M32 N01 N02 N03 N04 N05 N28 N29 N30 N31 N32 P01 P02 P03 P04 P05 P28 P29 P30 P31 P32 Signal GND GND GND N/C N/C PBCLK N/C PACLK VCC N/C GND TCK VCC VCC N/C GND N/C VCC TDI TDO VCC TMS TRST# N/C N/C N/C N/C N/C VCC N/C GND N/C VCC GND N/C VCC N/C GND Power Power Power Power Power Power I I I O Power 2.5V OD Power 2.5V 2.5V 14ma Power I Power 2.5V Power Power O LVTTL Power 10ma O LVTTL 10ma I/O Driver Type Power Power Power Driver Strength Internal Pullup/Pulldown
12-46
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# R01 R02 R03 R04 R05 R28 R29 R30 R31 R32 T01 T02 T03 T04 T05 T28 T29 T30 T31 T32 U01 U02 U03 U04 U05 U28 U29 U30 U31 U32 V01 V02 V03 V04 V05 V28 V29 V30 Signal VCC N/C GND N/C VCC GND N/C VCC N/C GND VCC N/C GND N/C VCC GND N/C VCC N/C GND N/C N/C N/C N/C N/C N/C N/C VCC N/C GND GND N/C VCC5A N/C GND VCC N/C VCC5N Power (PCI) Power Power I Power (PCI) Power Power Power Power Power Power Power Power Power Power Power Power Power Power I/O Driver Type Power Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-47
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# V31 V32 W01 W02 W03 W04 W05 W28 W29 W30 W31 W32 Y01 Y02 Y03 Y04 Y05 Y28 Y29 Y30 Y31 Y32 AA1 AA2 AA3 AA4 AA5 AA28 AA29 AA30 AA31 AA32 AB01 AB02 AB03 AB04 AB05 AB28 Signal N/C GND PBAD[31] PBAD[30] PBAD[29] PBAD[28] GND VCC PAAD[28] PAAD[29] PAAD[30] PAAD[31] VCC PBAD[27] GND PBAD[26] VCC VCC PAAD[26] GND PAAD[27] VCC PBAD[25] PBAD[24] PBAD[23] PBAD[22] PBAD[21] PAAD[21] PAAD[22] PAAD[23] PAAD[24] PAAD[25] GND PBAD[20] VCC5B PBAD[19] GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power PCI PCI PCI PCI Power Power PCI PCI PCI PCI Power PCI Power PCI Power Power PCI Power PCI Power PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI Power PCI Power (PCI) PCI Power Power I/O Driver Type Driver Strength Internal Pullup/Pulldown
12-48
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# AB29 AB30 AB31 AB32 AC01 AC02 AC03 AC04 AC05 AC28 AC29 AC30 AC31 AC32 AD01 AD02 AD03 AD04 AD05 AD28 AD29 AD30 AD31 AD32 AE01 AE02 AE03 AE04 AE05 AE28 AE29 AE30 AE31 AE32 AF01 AF02 AF03 AF04 Signal PAAD[19] VCC5M PAAD[20] GND PBAD[18] PBAD[17] PBAD[16] PBAD[15] PBAD[14] PAAD[14] PAAD[15] PAAD[16] PAAD[17] PAAD[18] VCC PBAD[13] GND PBAD[12] VCC VCC PAAD[12] GND PAAD[13] VCC PBAD[11] PBAD[10] PBAD[09] PBAD[08] PBAD[07] PAAD[07] PAAD[08] PAAD[09] PAAD[10] PAAD[11] GND PBAD[06] VCC5C PBAD[05] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type PCI Power (PCI) PCI Power PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI Power PCI Power PCI Power Power PCI Power PCI Power PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI Power PCI Power (PCI) PCI Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-49
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# AF05 AF28 AF29 AF30 AF31 AF32 AG01 AG02 AG03 AG04 AG05 AG28 AG29 AG30 AG31 AG32 AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 Signal GND GND PAAD[05] VCC5L PAAD[06] GND PBAD[04] PBAD[03] PBAD[02] PBAD[01] PBAD[00] PAAD[00] PAAD[01] PAAD[02] PAAD[03] PAAD[04] N/C N/C VCC5D VCC N/C N/C GND PBMON[01]# VCC PBGNT[02]# GND PBREQ[01]# VCC PBDEVSEL# GND PBCBE[00]# VCC PACBE[00]# GND PADEVSEL# VCC PAREQ[01]# I I/O I/O I/O I/O I O I/O Power LVTTL Power PCI Power PCI Power PCI Power PCI Power PCI Power PCI Power PCI 10ma Power (PCI) Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type Power Power PCI Power (PCI) PCI Power PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI Driver Strength Internal Pullup/Pulldown
12-50
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AJ01 AJ02 AJ03 AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 Signal GND PAGNT[02]# VCC PAMON[01]# GND N/C VCC VCC5K N/C N/C N/C N/C N/C VCC N/C N/C PBXARB# N/C PBRST# PBGNT[03]# PBGNT[00]# PBREQ[02]# PBCBE[03]# PBTRDY# PBLOCK# PBCBE[01]# REQ64# PACBE[01]# PALOCK# PATRDY# PACBE[03]# PAREQ[02]# PAGNT[00]# PAGNT[03]# PARST# MODE64# PAXARB# N/C O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O O I I PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI I PCI Power Power Power (PCI) I/O O I/O Driver Type Power PCI Power LVTTL Power 10ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-51
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# AJ29 AJ30 AJ31 AJ32 AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK08 AK09 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AL01 AL02 Signal VCC N/C N/C N/C N/C GND N/C VCC5E N/C N/C VCC N/C GND PBGNT[04]# VCC5F PBREQ[03]# GND PBIRDY# VCC5G PBPAR GND PAPAR VCC5H PAIRDY# GND PAREQ[03]# VCC5I PAGNT[04]# GND PHOLD# VCC N/C VCC5J N/C GND N/C N/C N/C Power Power (PCI) I O I I/O I/O I/O I/O I O Power PCI Power (PCI) PCI Power PCI Power (PCI) PCI Power PCI Power (PCI) PCI Power PCI Power (PCI) PCI Power PCI Power Power Power (PCI) Power I/O Driver Type Power Driver Strength Internal Pullup/Pulldown
12-52
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# AL03 AL04 AL05 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 Signal N/C N/C N/C N/C INTRQB# N/C PBMON[00]# PBGNT[05]# PBGNT[01]# PBREQ[04]# PBREQ[00]# PBFRAME# PBSTOP# PBSERR# ACK64# PASERR# PASTOP# PAFRAME# PAREQ[00]# PAREQ[04]# PAGNT[01]# PAGNT[05]# PAMON[00]# PHLDA# INTRQA# N/C N/C N/C N/C N/C N/C N/C GND GND GND N/C GND N/C Power Power Power Power I/O O O I I I/O I/O OD I/O OD I/O I/O I I O O I/O O OD PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI OD PCI I/O Driver Type Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-53
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued) PIN# AM09 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 Signal VCC N/C GND PBREQ[05]# VCC PBCBE[02]# GND PBPERR# VCC PAPERR# GND PACBE[02]# VCC PAREQ[05]# GND N/C VCC WSC# GND GND GND GND N/C GND Power Table 12-25: MUX Pin List Sorted by Pin Pin# A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 Signal GND Q2D23 Q1D22 Q3D21 Q3D20 GND Q3D19 VCC Q3D18 TDO VCC I/O O I/O I/O I/O I/O I/O I/O Driver Type Power LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL OD Power 10ma 14ma 10ma 10ma 10ma 10ma 10ma Driver Strength Internal Pullup/Pulldown O Power PCI Power Power Power Power I I/O I/O I/O I/O I Power PCI Power PCI Power PCI Power PCI Power PCI Power PCI Power I/O Driver Type Power Driver Strength Internal Pullup/Pulldown
12-54
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 C03 C04 C05 C06 C07 C08 C09 Signal Q3D17 VCC Q1D16 GND Q1D15 Q3D14 Q3D13 Q1D13 GND Q1D25 GND Q1D23 VCC Q2D21 GND Q2D19 VCC Q2D18 GND GND Q2D17 VCC Q0D16 GND Q2D14 VCC Q0D13 GND Q2D11 Q3D25 Q0D25 Q0D24 Q0D23 Q0D22 Q1D21 Q1D20 Q1D19 Q1D18 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL Power LVTTL Power LVTTL Power LVTTL Power Power LVTTL Power LVTTL Power LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Driver Strength 10ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-55
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 E05 E06 E07 Signal TDI TCK Q1D17 Q3D16 Q3D15 Q1D14 Q2D13 Q3D12 Q0D12 Q1D11 Q1D10 Q3D26 VCC Q3D24 GND Q3D22 VCC Q2D20 GND Q0D18 VCC VCC Q0D17 GND Q0D15 VCC Q2D12 GND Q0D11 VCC Q3D09 Q1D27 Q2D26 Q2D25 Q2D24 Q3D23 Q2D22 Q0D21 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL Power LVTTL Power LVTTL Power Power LVTTL Power LVTTL Power LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Driver Strength Internal Pullup/Pulldown
12-56
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F01 F02 F03 F04 F05 F06 F14 F15 F16 F17 F18 F19 F20 G01 G02 G03 G04 G05 G06 G16 G17 G18 G19 G20 H01 Signal Q0D20 Q0D19 TMS TRST# Q2D16 Q2D15 Q0D14 Q1D12 Q3D11 Q3D10 Q0D10 Q2D09 Q3D08 Q0D28 GND Q1D26 VCC Q1D24 VCC VCC VCC Q2D10 VCC Q1D09 GND Q1D08 Q2D28 Q1D28 Q3D27 Q0D27 Q0D26 VCC Q0D09 Q2D08 Q0D08 Q1D07 Q2D07 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL Power Power Power LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power LVTTL LVTTL LVTTL LVTTL LVTTL Power 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Driver Strength 10ma 10ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-57
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# H02 H03 H04 H05 H16 H17 H18 H19 H20 J01 J02 J03 J04 J05 J09 J10 J11 J12 J16 J17 J18 J19 J20 K01 K02 K03 K04 K05 K09 K10 K11 K12 K16 K17 K18 K19 K20 L01 Signal VCC Q0D29 GND Q2D27 Q3D07 GND Q0D07 VCC VCC Q0D30 Q3D29 Q2D29 Q1D29 Q3D28 GND GND GND GND Q3D06 Q3D05 Q0D06 Q1D06 Q2D06 Q3D30 GND Q2D30 VCC Q1D30 GND GND GND GND Q0D05 VCC Q1D05 GND Q2D05 Q2D31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type Power LVTTL Power LVTTL LVTTL Power LVTTL Power Power LVTTL LVTTL LVTTL LVTTL LVTTL Power Power Power Power LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL Power Power Power Power LVTTL Power LVTTL Power LVTTL LVTTL 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Driver Strength Internal Pullup/Pulldown
12-58
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# L02 L03 L04 L05 L09 L10 L11 L12 L16 L17 L18 L19 L20 M01 M02 M03 M04 M05 M09 M10 M11 M12 M16 M17 M18 M19 M20 N01 N02 N03 N04 N05 N16 N17 N18 N19 N20 P01 Signal GND Q1D31 VCC Q0D31 GND GND GND GND Q1D04 VCC Q2D04 GND Q3D04 Q2D32 Q1D32 Q0D32 Q3D31 Q3D32 GND GND GND GND Q3D02 Q1D03 Q2D03 Q3D03 Q0D04 VCC VCC Q0D33 GND Q3D33 Q3D01 GND Q0D03 VCC VCC Q2D33 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type Power LVTTL Power LVTTL Power Power Power Power LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power Power Power Power LVTTL LVTTL LVTTL LVTTL LVTTL Power Power LVTTL Power LVTTL LVTTL Power LVTTL Power Power LVTTL 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-59
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# P02 P03 P04 P05 P15 P16 P17 P18 P19 P20 R01 R02 R03 R04 R05 R06 R07 R15 R16 R17 R18 R19 R20 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 Signal Q1D33 Q0D34 Q1D34 Q3D34 VCC Q1D00 Q1D01 Q0D02 Q1D02 Q2D02 GND GND Q0D35 VCC MD31# VCC VCC VCC MD00# VCC Q2D00 GND GND Q2D34 Q1D35 Q3D35 MD32# MD29# DSTBP1# MD23# MD19# N/C VCCA WDME# CRES0 MD15# MD09# MD07# I I I/O I/O I/O Power AGTL+ Analog AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type LVTTL LVTTL LVTTL LVTTL Power LVTTL LVTTL LVTTL LVTTL LVTTL Power Power LVTTL Power AGTL+ Power Power Power AGTL+ Power LVTTL Power Power LVTTL LVTTL LVTTL AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 10ma 10ma 10ma 55ma 55ma 55ma 55ma 55ma 10ma 55ma 55ma 10ma 10ma 10ma 10ma 10ma 10ma Driver Strength 10ma 10ma 10ma 10ma Internal Pullup/Pulldown
12-60
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# T16 T17 T18 T19 T20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 Signal MD05# MD01# Q0D00 Q3D00 Q2D01 Q2D35 VCC MD33# GND VTT VCC MD21# GND VTT VCC VCC VTT GND MD13# VCC VTT GND MD02# VCC Q0D01 N/C MD34# MD30# MD27# VREF MD24# MD20# DOFF1# DOFF0# HCLKIN DVALID# LRD# CRES1 I/O I/O I/O I I/O I/O I I I I I I AGTL+ AGTL+ AGTL+ Analog AGTL+ AGTL+ AGTL+ AGTL+ 2.5V AGTL+ AGTL+ Analog 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type AGTL+ AGTL+ LVTTL LVTTL LVTTL LVTTL Power AGTL+ Power Power Power AGTL+ Power Power Power Power Power Power AGTL+ Power Power Power AGTL+ Power LVTTL 10ma 55ma 55ma 55ma 55ma Driver Strength 55ma 55ma 10ma 10ma 10ma 10ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-61
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# V14 V15 V16 V17 V18 V19 V20 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Signal MD16# MD10# VREF MD08# MD06# MD03# N/C MD35# GND VTT VCC MD25# GND VTT VCC DSEL# GND GND GDCMPLT# VCC VTT GND MD11# VCC VTT GND MD04# GND MD28# DSTBN1# MD26# MD22# GND MD18# LDSTB# MRESET# VCC WDEVT# I I/O I I I/O I/O I/O I/O I/O I/O I/O I I/O I/O AGTL+ Power Power Power AGTL+ Power Power Power AGTL+ Power Power AGTL+ Power Power Power AGTL+ Power Power Power AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ Power AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma I/O I/O I/O I I/O I/O I/O Driver Type AGTL+ AGTL+ Analog AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma Driver Strength 55ma 55ma Internal Pullup/Pulldown
12-62
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued) Pin# Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal AVWP# DCMPLT# MD17# GND MD14# MD12# DSTBP0# DSTBN0# GND I/O I/O I/O I/O I I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power Table 12-26: RCG Pin List Sorted by Pin Pin# A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06
Signal
Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma
Internal Pullup/Pulldown
I/O O O O O O O O O O O O O O O O O O
Driver Type Power LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL Power LVTTL Power
Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma
Internal Pullup/Pulldown
GND RASCA0# CASCA0# RASCB0# CASCB1# GND WECA# VCC WECB# ADDRD13 ADDRD08 ADDRD03 VCC ADDRD01 GND RASDD1# RASDD0# CASDC0# CASDA1# GND RASCA1# GND RASCB1# VCC CASCC0# GND
Intel(R) 450NX PCIset
12-63
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04
Signal
I/O O O
Driver Type LVTTL Power LVTTL Power Power
Driver Strength 10ma 10ma
Internal Pullup/Pulldown
CASCD1# VCC CASCC1# GND GND ADDRD04 VCC RASDC1# GND RASDC0# VCC CASDD1# GND CASDC1# ADDRC05 ADDRC03 ADDRC00 RASCC1# RASCC0# RASCD0# CASCB0# CASCD0# N/C ADDRD12 ADDRD09 ADDRD05 ADDRD02 ADDRD00 RASDA0# RASDB0# WEDA# CASDB0# CASDD0# WEDB# ADDRC08 VCC ADDRC02 GND
O O O O O O O O O O O O O O O O O O O O O O O O O O
LVTTL Power LVTTL Power LVTTL Power LVTTL Power LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power LVTTL Power
10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma
12-64
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F01 F02
Signal
I/O O O
Driver Type LVTTL Power LVTTL Power Power Power
Driver Strength 10ma 10ma
Internal Pullup/Pulldown
RASCD1# VCC CASCA1# GND N/C VCC VCC ADDRD06 GND RASDB1# VCC CASDA0# GND CASDB1# VCC N/C ADDRC10 ADDRC07 ADDRC04 ADDRC01 N/C N/C N/C N/C N/C ADDRD11 ADDRD10 ADDRD07 RASDA1# N/C N/C N/C N/C N/C N/C ADDRB12 ADDRC13 GND
O O O O
LVTTL Power LVTTL Power LVTTL Power LVTTL Power
10ma 10ma 10ma 10ma
O O O O
LVTTL LVTTL LVTTL LVTTL
10ma 10ma 10ma 10ma
O O O O
LVTTL LVTTL LVTTL LVTTL
10ma 10ma 10ma 10ma
O O
LVTTL LVTTL Power
10ma 10ma
Intel(R) 450NX PCIset
12-65
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# F03 F04 F05 F06 F14 F15 F16 F17 F18 F19 F20 G01 G02 G03 G04 G05 G06 G16 G17 G18 G19 G20 H01 H02 H03 H04 H05 H16 H17 H18 H19 H20 J01 J02 J03 J04 J05 J09
Signal
I/O O
Driver Type LVTTL LVTTL Power Power Power Power
Driver Strength 10ma 10ma
Internal Pullup/Pulldown
ADDRC06 VCC N/C VCC VCC VCC N/C VCC ADDRB13 GND ADDRB09 N/C ADDRC12 ADDRC11 ADDRC09 N/C VCC N/C ADDRB11 ADDRB10 ADDRB06 ADDRB05 VCC VCC CASAC0# GND CASAA1# ADDRB08 GND ADDRB07 VCC VCC WEAA# CASAB1# CASAD1# WEAB# CASAC1# GND O O O O O O O O O O O O O O O O O O
LVTTL Power LVTTL LVTTL LVTTL LVTTL Power LVTTL LVTTL LVTTL LVTTL Power Power LVTTL Power LVTTL LVTTL Power LVTTL Power Power LVTTL LVTTL LVTTL LVTTL LVTTL Power
10ma 10ma 10ma 10ma 10ma
10ma 10ma 10ma 10ma
10ma 10ma 10ma 10ma
10ma 10ma 10ma 10ma 10ma
12-66
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# J10 J11 J12 J16 J17 J18 J19 J20 K01 K02 K03 K04 K05 K09 K10 K11 K12 K16 K17 K18 K19 K20 L01 L02 L03 L04 L05 L09 L10 L11 L12 L16 L17 L18 L19 L20 M01 M02
Signal
I/O
Driver Type Power Power Power
Driver Strength
Internal Pullup/Pulldown
GND GND GND ADDRB04 ADDRB03 ADDRB02 ADDRB01 ADDRB00 CASAA0# GND CASAB0# VCC CASAD0# GND GND GND GND RASBB1# VCC RASBC1# GND RASBD1# RASAA0# GND RASAC0# VCC RASAD0# GND GND GND GND RASBA1# VCC RASBA0# GND RASBC0# RASAB0# RASAA1# O O O O O O O O O O O O O O O O O O O
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Power LVTTL Power LVTTL Power Power Power Power LVTTL Power LVTTL Power LVTTL LVTTL Power LVTTL Power LVTTL Power Power Power Power LVTTL Power LVTTL Power LVTTL LVTTL LVTTL
10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma
10ma 10ma 10ma 10ma 10ma 10ma
10ma 10ma 10ma 10ma 10ma
Intel(R) 450NX PCIset
12-67
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# M03 M04 M05 M09 M10 M11 M12 M16 M17 M18 M19 M20 N01 N02 N03 N04 N05 N16 N17 N18 N19 N20 P01 P02 P03 P04 P05 P15 P16 P17 P18 P19 P20 R01 R02 R03 R04 R05
Signal
I/O O O O
Driver Type LVTTL LVTTL LVTTL Power Power Power Power
Driver Strength 10ma 10ma 10ma
Internal Pullup/Pulldown
RASAB1# RASAC1# RASAD1# GND GND GND GND CASBA0# CASBB1# RASBB0# CASBB0# RASBD0# VCC VCC ADDRA01 GND ADDRA00 N/C GND CASBA1# VCC VCC ADDRA03 ADDRA02 ADDRA05 ADDRA04 N/C VCC N/C WEBA# CASBC0# CASBD0# WEBB# GND GND ADDRA06 VCC N/C
O O O O O
LVTTL LVTTL LVTTL LVTTL LVTTL Power Power
10ma 10ma 10ma 10ma 10ma
O O
LVTTL Power LVTTL Power
10ma 10ma
O
LVTTL Power Power
10ma
O O O O
LVTTL LVTTL LVTTL LVTTL Power
10ma 10ma 10ma 10ma
O O O O
LVTTL LVTTL LVTTL LVTTL Power Power
10ma 10ma 10ma 10ma
O
LVTTL Power
10ma
12-68
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# R06 R07 R15 R16 R17 R18 R19 R20 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10
Signal
I/O
Driver Type Power Power Power Power
Driver Strength
Internal Pullup/Pulldown
VCC VCC VCC N/C VCC CASBD1# GND GND ADDRA08 ADDRA07 ADDRA10 ADDRA09 N/C N/C MA05# MA02# N/C VCCA CMND1# BANK0# N/C WDME# LRD# N/C VCC BANKID# DR50T# CASBC1# ADDRA11 VCC N/C GND VTT VCC MA06# GND VTT VCC I I I O O O O I I I I O O O O O
LVTTL Power Power LVTTL LVTTL LVTTL LVTTL
10ma
10ma 10ma 10ma 10ma
LVTTL LVTTL Power AGTL+ AGTL+ AGTL+ AGTL+ Power LVTTL LVTTL LVTTL LVTTL Power Power Power Power LVTTL Power Power Power
10ma 10ma
55ma 55ma
Requires external pull-up 10ma 10ma
10ma
Intel(R) 450NX PCIset
12-69
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W01 W02 W03 W04 W05 W06 W07 W08
Signal
I/O
Driver Type Power Power Power
Driver Strength
Internal Pullup/Pulldown
VCC VTT GND RHIT# VCC VTT GND DR50H# VCC VCC ADDRA13 ADDRA12 CRES1 CRES0 VREF MA09# MA07# MA03# MA00# HCLKIN CSTB# BANK1# RCMPLT# PHIT# AVWP# VREF TRST# TCK TDO TDI N/C GND VTT VCC MA10# GND VTT VCC I O O I I I I I I I I I I O O O I I I O I I O
AGTL+ Power Power Power LVTTL Power Power LVTTL LVTTL Analog Analog Analog AGTL+ AGTL+ AGTL+ AGTL+ 2.5V AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Analog LVTTL LVTTL OD LVTTL Power Power Power AGTL+ Power Power Power
55ma
10ma 10ma
55ma 55ma 55ma
14ma
12-70
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued) Pin# W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
Signal
I/O I
Driver Type AGTL+ Power Power
Driver Strength
Internal Pullup/Pulldown
MA01# GND GND BANK2# VCC VTT GND N/C VCC VTT GND N/C GND N/C MA13# MA12# MA11# GND MA08# MA04# MRESET# VCC ROW# CMND0# CARD# GRCMPLT# GND LDSTB# N/C TMS N/C GND
I
AGTL+ Power Power Power Power Power Power Power
I I I I I I I I I I/O O I
AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ Power AGTL+ AGTL+ AGTL+ AGTL+ Power AGTL+ LVTTL Power 55ma 55ma
Intel(R) 450NX PCIset
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12. Electrical Characteristics
12.9.2
Pin Lists Sorted by Signal
Table 12-27: MIOC Pin List Sorted by Signal
Pin# B04 C04 D04 E04 A05 C05 E05 B06 C06 D06 A07 B07 C07 D07 E07 C08 E08 A09 B09 C09 D09 B10 D10 E10 B11 D11 A12 B12 C12 D12 E12 A13 B13 J03 K05 H01
Signal A03# A04# A05# A06# A07# A08# A09# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# AERR# AP0#
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma
Internal Pullup/Pulldown
12-72
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# J01 AJ17 AH18 AM18 D13 J29 C02 J30 J31 D01 J02 AL18 AJ18 AL11 AJ12 C11 A17 H29 AM12 D14 A15 B15 C15 D15 E15 B16 D16 E16 B17 D17 E17 A18 B18 C18 D18 E18 B19 D19 Signal AP1# BANK0# BANK1# BANK2# BERR# BINIT# BNR# BP0# BP1# BPRI# BR0# CARD0# CARD1# CMND0# CMND1# CRES0 CRES1 CRESET# CSTB# D00# D01# D02# D03# D04# D05# D06# D07# D08# D09# D10# D11# D12# D13# D14# D15# D16# D17# D18# I/O I/O O O O I/O I/O I/O I/O I/O I/O O O O O O I I O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ OD OD AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Analog Analog LVTTL AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 10ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 14ma 14ma 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
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12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# A20 B20 D20 A21 B21 C21 D21 E21 B22 D22 B23 D23 E23 A24 B24 C24 D24 C25 E25 A26 B26 C26 D26 E26 B27 C27 D27 A28 C28 E28 A29 B29 C29 D29 E29 B30 C30 E30 Signal D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
12-74
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# C31 D31 E31 D32 E32 F29 F30 A04 AJ16 AH15 G05 H32 H31 H30 G32 G31 G29 G28 F31 AH12 AM13 B14 AJ13 AL14 U02 AD01 AJ02 AH09 U01 AC04 AJ01 AK08 AK15 AL16 K01 K02 A01 A02 Signal D57# D58# D59# D60# D61# D62# D63# DBSY# DCMPLTA# DCMPLTB# DEFER# DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DOFF0# DOFF1# DRDY# DSEL0# DSEL1# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# DVALIDA# DVALIDB# ERR0# ERR1# GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O O O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ OD OD Power Power Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 14ma 14ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-75
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# A03 A06 A10 A11 A14 A16 A19 A22 A23 A27 B01 B02 B05 B28 C01 D08 D25 E09 E13 E14 E19 E20 E24 F01 F32 G01 H05 H28 J05 J32 L01 L32 M05 M28 R01 R29 T28 U04 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
12-76
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# U05 U32 V04 V05 V32 W05 Y28 AA05 AA28 AB01 AB32 AC01 AC05 AC28 AD05 AD28 AE01 AE32 AF01 AF32 AH13 AH14 AH19 AH20 AH24 AH25 AH32 AJ08 AJ19 AJ24 AJ25 AJ26 AK24 AK25 AK27 AK32 AL05 AL27 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-77
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# AL28 AL31 AL32 AM06 AM11 AM14 AM16 AM19 AM22 AM23 AM27 AM28 AM30 AM31 AM32 R28 G02 H02 N29 L04 N05 N04 F03 AM20 AL20 AJ20 AM21 AL21 AK21 AJ21 AH21 AL22 AJ22 AL23 AJ23 AH23 AM24 P02 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HCLKIN HIT# HITM# INIT# INTREQ# IOGNT# IOREQ# LOCK# MA00# MA01# MA02# MA03# MA04# MA05# MA06# MA07# MA08# MA09# MA10# MA11# MA12# MA13# MD00# OD O I O I O O O O O O O O O O O O O O I/O I I I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power 2.5V AGTL+ AGTL+ 2.5V LVTTL LVTTL LVTTL AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 10ma 14ma 10ma Driver Strength Internal Pullup/Pulldown
12-78
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# P03 P04 R02 R03 T01 T02 T03 T04 U03 V02 V03 W01 W02 W03 W04 Y02 Y04 Y05 AA01 AA02 AA03 AA04 AB02 AB04 AB05 AC02 AD02 AD03 AD04 AE02 AE04 AE05 AF02 AF04 AF05 AG01 AG02 AG03 Signal MD01# MD02# MD03# MD04# MD05# MD06# MD07# MD08# MD09# MD10# MD11# MD12# MD13# MD14# MD15# MD16# MD17# MD18# MD19# MD20# MD21# MD22# MD23# MD24# MD25# MD26# MD27# MD28# MD29# MD30# MD31# MD32# MD33# MD34# MD35# MD36# MD37# MD38# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-79
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# AG04 AH01 AH02 AH03 AH04 AH05 AJ04 AK02 AK03 AK04 AK05 AL03 AL04 AM04 AM05 AJ06 AK06 AL06 AH07 AJ07 AK07 AL07 AM07 AH08 AJ09 AK09 AL09 AM09 AJ10 AK10 AL10 AM10 AJ11 AL13 C23 K29 U28 AC32 Signal MD39# MD40# MD41# MD42# MD43# MD44# MD45# MD46# MD47# MD48# MD49# MD50# MD51# MD52# MD53# MD54# MD55# MD56# MD57# MD58# MD59# MD60# MD61# MD62# MD63# MD64# MD65# MD66# MD67# MD68# MD69# MD70# MD71# MRESET# N/C N/C N/C VCC Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
12-80
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# AK13 AL17 L31 P28 AM15 AJ15 E01 F04 G04 H04 F02 M29 AL12 AM17 AH16 J04 B03 C03 E03 E02 AL19 L03 M04 M03 L05 M01 N02 D02 L02 A30 A31 A32 B31 B32 C10 C13 C14 C19 Signal PHITA# PHITB# PWRGD PWRGDB RCMPLTA# RCMPLTB# REQ0# REQ1# REQ2# REQ3# REQ4# RESET# RHITA# RHITB# ROW# RP# RS0# RS1# RS2# RSP# SMIACT# TCK TDI TDO TMS TPCTL0 TPCTL1 TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC I I I O I I I/O I/O I/O I/O I/O I/O I I O I/O I/O I/O I/O I/O O I I O I I I I/O I I/O Driver Type AGTL+ AGTL+ LVTTL LVTTL AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ LVTTL LVTTL LVTTL OD LVTTL LVTTL LVTTL AGTL+ LVTTL Power Power Power Power Power Power Power Power Power 55ma 14ma 55ma 55ma 55ma 55ma 55ma 55ma 10ma 55ma 55ma 55ma 55ma 55ma 55ma 10ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-81
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# C20 C22 C32 E06 E27 F05 F28 K03 K28 L30 M02 N01 N32 P01 P05 P32 R04 R05 T05 V01 V28 V29 W28 Y01 Y32 AB03 AB30 AC30 AF28 AG05 AG28 AH06 AH10 AH11 AH17 AH27 AK01 AK11 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
12-82
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# AK12 AK14 AK18 AK19 AK20 AK22 AK23 AL01 AL02 AL24 AM01 AM02 AM03 K30 K31 K32 K04 N31 U30 AC03 AG29 AL15 A08 A25 B08 B25 C16 C17 D03 D05 D28 D30 E11 E22 G03 G30 H03 N03 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA0 VCCA1 VCCA2 VREF VREF VREF VREF VREF VREF VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT I I I I I I I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Analog Analog Analog Analog Analog Analog Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-83
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# Y03 Y30 AE03 AE30 AF03 AF30 AH22 AJ03 AJ05 AJ28 AJ30 AK16 AK17 AL08 AL25 AL26 AM08 AM25 AM26 AJ14 R30 P31 P30 R32 L28 L29 J28 T32 T31 T30 T29 U29 U31 Y31 Y29 AA32 AA31 AA30 Signal VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT WDEVT# X0ADS# X0BE0# X0BE1# X0BLK# X0CLK X0CLKB X0CLKFB X0D00# X0D01# X0D02# X0D03# X0D04# X0D05# X0D06# X0D07# X0D08# X0D09# X0D10# O I/O I/O I/O O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ LVTTL LVTTL LVTTL AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 10ma 10ma Driver Strength Internal Pullup/Pulldown
12-84
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# AA29 AB31 AB29 AB28 AC31 W30 W31 W32 R31 P29 N30 M32 W29 V30 V31 AD32 AD30 AD29 AE28 M30 M31 N28 AE31 AE29 AF31 AF29 AG31 AG30 AJ29 AK31 AK30 AK29 AK28 AL30 AL29 AJ27 AH26 AK26 Signal X0D11# X0D12# X0D13# X0D14# X0D15# X0HRTS# X0HSTBN# X0HSTBP# X0PAR# X0RST# X0RSTB# X0RSTFB# X0XRTS# X0XSTBN# X0XSTBP# X1ADS# X1BE0# X1BE1# X1BLK# X1CLK X1CLKB X1CLKFB X1D00# X1D01# X1D02# X1D03# X1D04# X1D05# X1D06# X1D07# X1D08# X1D09# X1D10# X1D11# X1D12# X1D13# X1D14# X1D15# I/O I/O I/O I/O I/O I/O O O O I/O O O I I I I I/O I/O I/O O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ LVTTL LVTTL LVTTL AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 10ma 10ma Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-85
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued) Pin# AJ32 AH28 AH29 AM29 AC29 AD31 AG32 AJ31 AH30 AH31 Signal X1HRTS# X1HSTBN# X1HSTBP# X1PAR# X1RST# X1RSTB# X1RSTFB# X1XRTS# X1XSTBN# X1XSTBP# I/O O O O I/O O O I I I I Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Table 12-28: PXB Pin List Sorted by Signal PIN# AL17 E09 D09 AL27 AL7 AJ26 A01 A02 A11 A13 A23 A25 A30 A31 A32 B01 B05 B06 B07 B08 B09 B10 B11 B12 B13 Signal ACK64# CRES0 CRES1 INTRQA# INTRQB# MODE64# N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C I/O I/O I I OD OD I Driver Type PCI Analog Analog PCI PCI PCI Driver Strength Internal Pullup/Pulldown Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
12-86
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# B17 B23 B24 B25 B26 B27 B32 C01 C02 C03 C04 C05 C09 C11 C13 C23 C28 C29 C30 C31 C32 D01 D03 D05 D06 D07 D08 D10 D11 D12 D13 D14 D19 D23 D24 D25 D26 D30 Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C I/O Driver Type Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-87
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# D32 E01 E02 E03 E04 E05 E07 E11 E25 E28 E29 E30 E31 E32 F02 F04 F30 F32 G01 G02 G03 G04 G05 G28 G29 G32 H02 H04 H28 H29 H31 H32 J01 J02 J03 J04 J05 J28 Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C I/O Driver Type Driver Strength Internal Pullup/Pulldown
12-88
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# J29 J31 K02 K04 K31 L28 L29 L31 M02 M31 N28 N29 N30 N31 N32 P02 P04 P29 P31 R02 R04 R29 R31 T02 T04 T29 T31 U01 U02 U03 U04 U05 U28 U29 U31 V02 V04 V29 Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C I/O Driver Type Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-89
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# V31 AH01 AH02 AH05 AH06 AH28 AH31 AH32 AJ01 AJ02 AJ03 AJ05 AJ06 AJ08 AJ28 AJ30 AJ31 AJ32 AK01 AK03 AK05 AK06 AK08 AK28 AK30 AK32 AL01 AL02 AL03 AL04 AL05 AL06 AL08 AL28 AL29 AL30 AL31 AL32 Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C I/O Driver Type Driver Strength Internal Pullup/Pulldown
12-90
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# AM01 AM02 AM06 AM08 AM10 AM24 AM31 K29 M29 F31 AG28 AG29 AG30 AG31 AG32 AF29 AF31 AE28 AE29 AE30 AE31 AE32 AD29 AD31 AC28 AC29 AC30 AC31 AC32 AB29 AB31 AA28 AA29 AA30 AA31 AA32 Y29 Y31 Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C PAAD[00] PAAD[01] PAAD[02] PAAD[03] PAAD[04] PAAD[05] PAAD[06] PAAD[07] PAAD[08] PAAD[09] PAAD[10] PAAD[11] PAAD[12] PAAD[13] PAAD[14] PAAD[15] PAAD[16] PAAD[17] PAAD[18] PAAD[19] PAAD[20] PAAD[21] PAAD[22] PAAD[23] PAAD[24] PAAD[25] PAAD[26] PAAD[27] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI I/O Driver Type Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-91
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# W29 W30 W31 W32 AH18 AJ18 AM20 AJ21 L32 J32 AH20 AL20 AJ23 AL23 AH24 AJ24 AK24 AL24 AK20 AJ19 AL25 AH26 AK18 AM18 AL21 AH22 AJ22 AK22 AL22 AM22 AJ25 AL18 AL19 AJ20 AJ27 AG05 AG04 AG03 Signal PAAD[28] PAAD[29] PAAD[30] PAAD[31] PACBE[0]# PACBE[1]# PACBE[2]# PACBE[3]# PACLK PACLKFB PADEVSEL# PAFRAME# PAGNT[0]# PAGNT[1]# PAGNT[2]# PAGNT[3]# PAGNT[4]# PAGNT[5]# PAIRDY# PALOCK# PAMON[0]# PAMON[1]# PAPAR PAPERR# PAREQ[0]# PAREQ[1]# PAREQ[2]# PAREQ[3]# PAREQ[4]# PAREQ[5]# PARST# PASERR# PASTOP# PATRDY# PAXARB# PBAD[00] PBAD[01] PBAD[02] I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I/O I/O O O O O O O I/O I/O I/O I/O I/O I/O I I I I I I O OD I/O I/O I I/O I/O I/O Driver Type PCI PCI PCI PCI PCI PCI PCI PCI LVTTL LVTTL PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI LVTTL LVTTL PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI 10ma 10ma 10ma Driver Strength Internal Pullup/Pulldown
12-92
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# AG02 AG01 AF04 AF02 AE05 AE04 AE03 AE02 AE01 AD04 AD02 AC05 AC04 AC03 AC02 AC01 AB04 AB02 AA05 AA04 AA03 AA02 AA01 Y04 Y02 W04 W03 W02 W01 AH16 AJ16 AM14 AJ13 L30 J30 AH14 AL14 AJ11 Signal PBAD[03] PBAD[04] PBAD[05] PBAD[06] PBAD[07] PBAD[08] PBAD[09] PBAD[10] PBAD[11] PBAD[12] PBAD[13] PBAD[14] PBAD[15] PBAD[16] PBAD[17] PBAD[18] PBAD[19] PBAD[20] PBAD[21] PBAD[22] PBAD[23] PBAD[24] PBAD[25] PBAD[26] PBAD[27] PBAD[28] PBAD[29] PBAD[30] PBAD[31] PBCBE[0]# PBCBE[1]# PBCBE[2]# PBCBE[3]# PBCLK PBCLKFB PBDEVSEL# PBFRAME# PBGNT[0]# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I/O I/O O Driver Type PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI LVTTL LVTTL PCI PCI PCI 10ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-93
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# AL11 AH10 AJ10 AK10 AL10 AK14 AJ15 AL09 AH08 AK16 AM16 AL13 AH12 AJ12 AK12 AL12 AM12 AJ09 AL16 AL15 AJ14 AJ07 AL26 AK26 F29 D29 AJ17 M04 N01 N02 N04 N05 A03 A04 A05 A06 A07 A08 Signal PBGNT[1]# PBGNT[2]# PBGNT[3]# PBGNT[4]# PBGNT[5]# PBIRDY# PBLOCK# PBMON[0]# PBMON[1]# PBPAR PBPERR# PBREQ[0]# PBREQ[1]# PBREQ[2]# PBREQ[3]# PBREQ[4]# PBREQ[5]# PBRST# PBSERR# PBSTOP# PBTRDY# PBXARB# PHLDA# PHOLD# PIIXOK# PWRGD REQ64# TCK TDI TDO TMS TRST# VCC VCC VCC VCC VCC VCC I/O O O O O O I/O I/O I/O I/O I/O I/O I I I I I I O OD I/O I/O I O I I I I/O I I O I I Driver Type PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI LVTTL LVTTL PCI 2.5V 2.5V OD 2.5V 2.5V Power Power Power Power Power Power 14ma Driver Strength Internal Pullup/Pulldown
12-94
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# A09 A10 A14 A16 A18 A20 A22 A26 A28 A29 B02 B03 B04 B28 B29 B30 B31 D27 F03 G30 G31 H01 H05 K03 K30 M01 M05 M28 M32 N03 P01 P30 R01 R30 T01 T30 U030 Y1 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-95
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# Y05 Y28 Y32 AD01 AD05 AD28 AD32 AH04 AH09 AH13 AH17 AH21 AH25 AH29 AJ04 AJ29 AK07 AK27 AM09 AM13 AM17 AM21 AM25 P05 R05 T05 V28 W28 V03 AB03 AF03 AH03 AK04 AK11 AK15 AK19 AK23 AK29 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC5A VCC5B VCC5C VCC5D VCC5E VCC5F VCC5G VCC5H VCC5I VCC5J I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power (PCI) Power (PCI) Power (PCI) Power (PCI) Power (PCI) Power (PCI) Power (PCI) Power (PCI) Power (PCI) Power (PCI) Driver Strength Internal Pullup/Pulldown
12-96
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# AH30 AF30 AB30 V30 A27 C27 E27 A12 A24 C06 C07 C08 C10 C12 C14 C16 C18 C20 C22 C24 C26 D02 D31 F01 F05 F28 H03 H30 K01 K05 K28 K32 L01 L02 L03 L04 L05 M03 Signal VCC5K VCC5L VCC5M VCC5N VCCA0 VCCA1 VCCA2 VREF VREF GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I I I/O Driver Type Power (PCI) Power (PCI) Power (PCI) Power (PCI) Power Power Power Analog Analog Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-97
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# M30 P03 P32 R03 R32 T03 T32 U32 V01 V32 Y03 Y30 AB01 AB05 AB28 AB32 AD03 AD30 AF01 AF05 AF28 AF32 AH07 AH11 AH15 AH19 AH23 AH27 AK02 AK09 AK13 AK17 AK21 AK25 AK31 AM03 AM04 AM05 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
12-98
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# AM07 AM11 AM15 AM19 AM23 AM27 AM28 AM29 AM30 AM32 P28 R28 T28 V05 W05 D04 D28 E06 E08 E10 E12 E14 E16 E18 E20 E22 E24 E26 AM26 C21 E23 B22 A21 C25 D21 E21 B20 D20 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT WSC# XADS# XBE[0]# XBE[1]# XBLK# XCLK XD[00]# XD[01]# XD[02]# XD[03]# O I/O I/O I/O I I I/O I/O I/O I/O I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power PCI AGTL+ AGTL+ AGTL+ AGTL+ LVTTL AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-99
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued) PIN# A19 B19 D17 E17 B16 D16 A15 B15 C15 D15 E15 B14 B18 A17 C17 E13 B21 D22 D18 C19 E19 Signal XD[04]# XD[05]# XD[06]# XD[07]# XD[08]# XD[09]# XD[10]# XD[11]# XD[12]# XD[13]# XD[14]# XD[15]# XHRTS# XHSTBN# XHSTBP# XIB XPAR# XRST# XXRTS# XXSTBN# XXSTBP# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O I/O I O O O Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Internal Pullup/Pulldown
Table 12-29: MUX Pin List Sorted by Signal PIN# Y12 T12 V13 Y13 V09 V08 W09 Y19 Y03 Y18 T06 V11 T09 Signal AVWP# CRES0 CRES1 DCMPLT# DOFF0# DOFF1# DSEL# DSTBN0# DSTBN1# DSTBP0# DSTBP1# DVALID# N/C I I I I/O I I I I/O I/O I/O I/O I I/O Driver Type AGTL+ Analog Analog AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma Driver Strength Input Pullup/Pulldown
12-100
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# W12 A01 A06 A15 A20 B02 B06 B10 B11 B15 B19 F02 F19 H04 H17 J09 J10 J11 J12 N04 N17 R01 R02 R19 R20 W06 W10 W11 W15 W19 Y01 Y06 Y15 Y20 D04 D08 D13 D17 Signal GDCMPLT# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O I/O Driver Type AGTL+ Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength 55ma Input Pullup/Pulldown
Intel(R) 450NX PCIset
12-101
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# K02 K09 K10 K11 K12 K19 L02 L09 L10 L11 L12 L19 M09 M10 M11 M12 U04 U08 U13 U17 W02 V10 Y08 V12 R16 T17 U18 V19 W20 T16 V18 T15 V17 T14 V15 W16 Y17 U14 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HCLKIN LDSTB# LRD# MD00# MD01# MD02# MD03# MD04# MD05# MD06# MD07# MD08# MD09# MD10# MD11# MD12# MD13# I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power 2.5V AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Driver Strength Input Pullup/Pulldown
12-102
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# Y16 T13 V14 Y14 Y07 T08 V07 U07 Y05 T07 V06 W05 Y04 V04 Y02 T05 V03 R05 T04 U03 V02 W01 Y09 Y10 V20 V01 T18 U20 P18 N18 M20 K16 J18 H18 G18 G16 E18 D18 Signal MD14# MD15# MD16# MD17# MD18# MD19# MD20# MD21# MD22# MD23# MD24# MD25# MD26# MD27# MD28# MD29# MD30# MD31# MD32# MD33# MD34# MD35# MRESET# VCC N/C N/C Q0D00 Q0D01 Q0D02 Q0D03 Q0D04 Q0D05 Q0D06 Q0D07 Q0D08 Q0D09 Q0D10 Q0D11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Driver Type AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power Driver Strength 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma 55ma Input Pullup/Pulldown
Intel(R) 450NX PCIset
12-103
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# C18 B18 E14 D14 B14 D12 D09 E09 E08 E07 C05 C04 C03 C02 G05 G04 F01 H03 J01 L05 M03 N03 P03 R03 P16 P17 P19 M17 L16 K18 J19 G19 F20 F18 C20 C19 E15 A19 Signal Q0D12 Q0D13 Q0D14 Q0D15 Q0D16 Q0D17 Q0D18 Q0D19 Q0D20 Q0D21 Q0D22 Q0D23 Q0D24 Q0D25 Q0D26 Q0D27 Q0D28 Q0D29 Q0D30 Q0D31 Q0D32 Q0D33 Q0D34 Q0D35 Q1D00 Q1D01 Q1D02 Q1D03 Q1D04 Q1D05 Q1D06 Q1D07 Q1D08 Q1D09 Q1D10 Q1D11 Q1D12 Q1D13 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Input Pullup/Pulldown
12-104
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# C15 A16 A14 C12 C09 C08 C07 C06 A03 B03 F05 B01 F03 E01 G02 J04 K05 L03 M02 P02 P04 T02 R18 T20 P20 M18 L18 K20 J20 G20 G17 E19 F16 B20 D16 C16 B16 E13 Signal Q1D14 Q1D15 Q1D16 Q1D17 Q1D18 Q1D19 Q1D20 Q1D21 Q1D22 Q1D23 Q1D24 Q1D25 Q1D26 Q1D27 Q1D28 Q1D29 Q1D30 Q1D31 Q1D32 Q1D33 Q1D34 Q1D35 Q2D00 Q2D01 Q2D02 Q2D03 Q2D04 Q2D05 Q2D06 Q2D07 Q2D08 Q2D09 Q2D10 Q2D11 Q2D12 Q2D13 Q2D14 Q2D15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Input Pullup/Pulldown
Intel(R) 450NX PCIset
12-105
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# E12 B12 B09 B07 D07 B05 E06 A02 E04 E03 E02 H05 G01 J03 K03 L01 M01 P01 T01 U01 T19 N16 M16 M19 L20 J17 J16 H16 E20 D20 E17 E16 C17 A18 A17 C14 C13 A12 Signal Q2D16 Q2D17 Q2D18 Q2D19 Q2D20 Q2D21 Q2D22 Q2D23 Q2D24 Q2D25 Q2D26 Q2D27 Q2D28 Q2D29 Q2D30 Q2D31 Q2D32 Q2D33 Q2D34 Q2D35 Q3D00 Q3D01 Q3D02 Q3D03 Q3D04 Q3D05 Q3D06 Q3D07 Q3D08 Q3D09 Q3D10 Q3D11 Q3D12 Q3D13 Q3D14 Q3D15 Q3D16 Q3D17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Input Pullup/Pulldown
12-106
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# A09 A07 A05 A04 D05 E05 D03 C01 D01 G03 J05 J02 K01 M04 M05 N05 P05 T03 C11 C10 A10 E10 E11 A08 A11 A13 B04 B08 B13 B17 F04 F06 F14 F15 F17 G06 H01 H02 Signal Q3D18 Q3D19 Q3D20 Q3D21 Q3D22 Q3D23 Q3D24 Q3D25 Q3D26 Q3D27 Q3D28 Q3D29 Q3D30 Q3D31 Q3D32 Q3D33 Q3D34 Q3D35 TCK TDI TDO TMS TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O I I Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL OD LVTTL LVTTL Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power 14ma Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Input Pullup/Pulldown
Intel(R) 450NX PCIset
12-107
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# H19 H20 N19 N20 P15 R04 R06 R07 R15 R17 W08 W13 W17 D02 D06 D10 D11 D15 D19 K04 K17 L04 L17 N01 N02 U02 U06 U10 U11 U15 U19 W04 T10 V05 V16 W07 W14 W18 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VREF VREF VTT VTT VTT I I I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Analog Analog Power Power Power Driver Strength Input Pullup/Pulldown
12-108
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued) PIN# U05 U09 U12 U16 W03 Y11 T11 Signal VTT VTT VTT VTT VTT WDEVT# WDME# I I I/O Driver Type Power Power Power Power Power AGTL+ AGTL+ Table 12-30: RCG Pin List Sorted by Signal Pin# N05 N03 P02 P01 P04 P03 R03 T02 T01 T04 T03 U01 V02 V01 J20 J19 J18 J17 J16 G20 G19 H18 H16 F20 G18 G17 E20 F18 Signal ADDRA00 ADDRA01 ADDRA02 ADDRA03 ADDRA04 ADDRA05 ADDRA06 ADDRA07 ADDRA08 ADDRA09 ADDRA10 ADDRA11 ADDRA12 ADDRA13 ADDRB00 ADDRB01 ADDRB02 ADDRB03 ADDRB04 ADDRB05 ADDRB06 ADDRB07 ADDRB08 ADDRB09 ADDRB10 ADDRB11 ADDRB12 ADDRB13 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Internal Pullup/Pulldown Driver Strength Input Pullup/Pulldown
Intel(R) 450NX PCIset
12-109
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# C03 E04 D03 C02 E03 C01 F03 E02 D01 G04 E01 G03 G02 F01 C14 A14 C13 A12 B12 C12 D12 E12 A11 C11 E11 E10 C10 A10 V15 T12 V12 W12 T18 Y13 K01 H05 K03 J02 Signal ADDRC00 ADDRC01 ADDRC02 ADDRC03 ADDRC04 ADDRC05 ADDRC06 ADDRC07 ADDRC08 ADDRC09 ADDRC10 ADDRC11 ADDRC12 ADDRC13 ADDRD00 ADDRD01 ADDRD02 ADDRD03 ADDRD04 ADDRD05 ADDRD06 ADDRD07 ADDRD08 ADDRD09 ADDRD10 ADDRD11 ADDRD12 ADDRD13 AVWP# BANK0# BANK1# BANK2# BANKID# CARD# CASAA0# CASAA1# CASAB0# CASAB1# I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I I I I I O O O O Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL AGTL+ AGTL+ AGTL+ AGTL+ LVTTL AGTL+ LVTTL LVTTL LVTTL LVTTL 10ma 10ma 10ma 10ma Requires external pull-up Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 55ma Internal Pullup/Pulldown
12-110
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# H03 J05 K05 J03 M16 N18 M19 M17 P18 T20 P19 R18 A03 D07 C07 A05 B05 B09 C08 B07 D16 A19 C18 D18 A18 B20 C19 B18 Y12 T11 V04 V03 V11 U18 T19 A01 A06 A15 Signal CASAC0# CASAC1# CASAD0# CASAD1# CASBA0# CASBA1# CASBB0# CASBB1# CASBC0# CASBC1# CASBD0# CASBD1# CASCA0# CASCA1# CASCB0# CASCB1# CASCC0# CASCC1# CASCD0# CASCD1# CASDA0# CASDA1# CASDB0# CASDB1# CASDC0# CASDC1# CASDD0# CASDD1# CMND0# CMND1# CRES0 CRES1 CSTB# DR50H# DR50T# GND GND GND I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O 0 I I I I I I I Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL AGTL+ AGTL+ Analog Analog AGTL+ LVTTL LVTTL Power Power Power Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-111
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# A20 B02 B06 B10 B11 B15 B19 F02 F19 H04 H17 J09 J10 J11 J12 N04 N17 R01 R02 R19 R20 W06 W10 W11 W15 W19 Y01 Y06 Y15 Y20 D04 D08 D13 D17 K02 K09 K10 K11 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
12-112
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# K12 K19 L02 L09 L10 L11 L12 L19 M09 M10 M11 M12 U04 U08 U13 U17 W02 Y14 V10 Y16 T15 V09 W09 T08 V08 Y08 T07 U07 V07 Y07 V06 W05 Y05 Y04 Y03 Y09 T17 P16 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GRCMPLT# HCLKIN LDSTB# LRD# MA00# MA01# MA02# MA03# MA04# MA05# MA06# MA07# MA08# MA09# MA10# MA11# MA12# MA13# MRESET# VCC N/C I/O I O O I I I I I I I I I I I I I I I I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power AGTL+ 2.5V AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power 55ma 55ma 55ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-113
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# R05 R16 T05 T06 T09 T13 T16 E05 E06 E07 E08 E09 E14 E15 E16 F05 F16 G05 G16 N16 P05 Y10 C09 D09 D20 E17 E18 E19 G01 W1 W16 W20 Y02 U03 Y17 Y19 V14 L01 Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C VCC N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C PHIT# RASAA0# O O AGTL+ LVTTL 55ma 10ma Power I/O Driver Type Driver Strength Internal Pullup/Pulldown
12-114
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# M02 M01 M03 L03 M04 L05 M05 L18 L16 M18 K16 L20 K18 M20 K20 A02 B01 A04 B03 C05 C04 C06 D05 C15 E13 C16 D14 B16 B14 A17 A16 V13 U14 Y11 V18 V20 V19 Y18 Signal RASAA1# RASAB0# RASAB1# RASAC0# RASAC1# RASAD0# RASAD1# RASBA0# RASBA1# RASBB0# RASBB1# RASBC0# RASBC1# RASBD0# RASBD1# RASCA0# RASCA1# RASCB0# RASCB1# RASCC0# RASCC1# RASCD0# RASCD1# RASDA0# RASDA1# RASDB0# RASDB1# RASDC0# RASDC1# RASDD0# RASDD1# RCMPLT# RHIT# ROW# TCK TDI TDO TMS I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I I I O I Driver Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL AGTL+ AGTL+ AGTL+ LVTTL LVTTL OD LVTTL 14ma Driver Strength 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 55ma 55ma Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-115
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# V17 D11 D15 D19 K04 K17 L04 L17 N01 N02 U02 U06 U10 U11 U15 U19 U20 W04 A08 A13 B04 B08 B13 B17 F04 F06 F14 F15 F17 G06 H01 H02 H19 H20 N19 N20 P15 R04 Signal TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC I I/O Driver Type LVTTL Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Driver Strength Internal Pullup/Pulldown
12-116
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued) Pin# R06 R07 R15 R17 W08 W13 W17 D02 D06 D10 T10 V05 V16 W07 W14 W18 U05 U09 U12 U16 W03 T14 J01 J04 P17 P20 A07 A09 C17 C20 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VREF VREF VTT VTT VTT VTT VTT VTT VTT VTT WDME# WEAA# WEAB# WEBA# WEBB# WECA# WECB# WEDA# WEDB# O O O O O O O O O I I I/O Driver Type Power Power Power Power Power Power Power Power Power Power Power Analog Analog Power Power Power Power Power Power Power Power AGTL+ LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL 55ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma 10ma Driver Strength Internal Pullup/Pulldown
Intel(R) 450NX PCIset
12-117
12. Electrical Characteristics
12.9.3
12.9.3.1
Package information
324 BGA Package Information
NOTE:
Measurements in millimeters
Figure 12-15: 324 BGA Dimension Top View
12-118
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Figure 12-16: 324 BGA Dimensions Bottom View
Intel(R) 450NX PCIset
12-119
12. Electrical Characteristics
12.9.3.2
540 PBGA Package Information
12-120
Intel(R) 450NX PCIset
12.9 Mechanical Specifications
Table 12-31: 540 PBGA dimensions Package Dimensions Packages 540 LD Symbol A A1 A2 b c D D1 E E1 e N S1 3.59 0.40 0.95 0.60 2.00 42.30 42.30 1.27 540 1.56 REF
NOTE: Measurement in millimeters
Min 4.10 0.70 1.10 0.90 2.30 42.70 27.70 42.70 27.70
Max
Intel(R) 450NX PCIset
12-121
12. Electrical Characteristics
AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Bottom View
Figure 12-17: 540 PBGA Pin Grid
12-122
Intel(R) 450NX PCIset
UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119 Tel: +1 408 765-8080 JAPAN, Intel Japan K.K. 5-6 Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: + 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. 1, Quai de Grenelle, 75015 Paris Tel: +33 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd. Pipers Way, Swindon, Wiltshire, England SN3 1RJ Tel: +44 1-793-641440 GERMANY, Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/ Muenchen Tel: +49 89/99143-0 HONG KONG, Intel Semiconductor Ltd. 32/F Two Pacific Place, 88 Queensway, Central Tel: +852 2844-4555 CANADA, Intel Semiconductor of Canada, Ltd. 190 Attwell Drive, Suite 500 Rexdale, Ontario M9W 6H8 Tel: +416 675-2438


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